16
Specifications ispGDX240VA
Boundary Scan
The ispGDXVA devices provide IEEE1149.1a test capa-
bility and ISP programming through a standard Boundary
Scan Test Access Port (TAP) interface.
The boundary scan circuitry on the ispGDXVA Family
operates independently of the programmed pattern. This
allows customers using boundary scan test to have full
test capability with only a single BSDL file.
Table 2. I/O Shift Register Order
I/O Shift Reg Order/ispGDX240
ispGDX240VA TDI, TOE, Y2, Y3, RESET, Y1, Y0, I/O B30 .. B59, I/O C0 .. C59, I/O D0 .. D29, I/O B29 .. B0,
I/O A59.. A0, I/O D59 .. D30, TDO
I/O SHIFT REGISTER ORDER
DEVICE
Table 3. ispGDX240VA Device ID Codes
ID Code/GDX240VA
ispGDX240VA 0001, 0000, 0011, 0101, 0100, 0000, 0100, 0011
32-BIT BOUNDARY SCAN ID CODE
DEVICE
The ispGDXVA devices are identified by the 32-bit JTAG
IDCODE register. The device ID assignments are listed
in Table 3.
The ispJTAG programming is accomplished by execut-
ing Lattice private instructions under the Boundary Scan
State Machine.
Contact Lattice Applications to obtain more detailed
programming information.
Figure 7. Boundary Scan I/O Register Cell
D
Q
M
U
X
D
Q
D
Q
D
Q
D
Q
M
U
X
M
U
X
M
U
X
M
U
X
Normal
Function
OE
I/O Pin
EXTEST
Update DR
SCANOUT (to next cell)
Clock DR
SCANIN
(from
previous
cell)
Shift DR
Normal
Function
OE
TOE
17
Specifications ispGDX240VA
1
0
0
1
1
0
0
1
0
0
0
0
1
0
1
1
0101
1
1
0
1
0
0
111
0
0
1
Update-IR
Exit2-IR
Pause-IR
Exit1-IR
Shift-IR
Capture-IR
Select-IR-Scan
Update-DR
Exit2-DR
Pause-DR
Exit1-DR
Shift-DR
Capture-DR
Select-DR-Scan
Run-Test/Idle
Test-Logic-Reset
TCK
TMS or
TDI
TDO
tsu th
tco
tsu = 0.1µs (min.) th = 0.1µs (min.) tco = 0.1µs (min.)
Figure 8. Boundary Scan State Machine
18
Specifications ispGDX240VA
I/O Input/Output Pins – These are the general purpose bidirectional data pins. When used as outputs,
each may be independently latched, registered or tristated. They can also each assume one other
control function (OE, CLK/CLKEN, and MUXsel as described in the text).
TOE Test Output Enable Pin – This pin tristates all I/O pins when a logic low is driven.
RESET Active LOW Input Pin – Resets all I/O register outputs when LOW.
Yx/CLKENx Input Pins –These can be either Global Clocks or Clock Enables.
EPEN Input Pin – JTAG TAP Controller Enable Pin. When high, JTAG operation is enabled. When low,
JTAG TAP controller is driven to reset.
TDI Input Pin – Serial data input during ISP programming or Boundary Scan mode.
TCK Input Pin – Serial data clock during ISP programming or Boundary Scan mode.
TMS Input Pin – Control input during ISP programming or Boundary Scan mode.
TDO Output Pin – Serial data output during ISP programming or Boundary Scan mode.
GND Ground (GND)
VCC Vcc – Supply voltage (3.3V).
VCCIO Input – This pin is used if optional 2.5V output is to be used. Every I/O can independently select either
3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin
must be connected to the VCC supply. Programmable pull-up resistors and bus-hold latches only draw
current from this supply.
NC
1
No Connect.
Signal Descriptions
Signal Name Description
1. NC pins are not to be connected to any active signals, VCC or GND.
Signal Locations: ispGDX240VA
Signal 388-Ball fpBGA
TOE L22
RESET L21
Y0/CLKEN0 M4
Y1/CLKEN1 L3
Y2/CLKEN2 M20
Y3/CLKEN3 M21
EPEN A11
TDI M1
TCK L1
TMS L2
TDO AB12
GND A1, A22, B2, B21, C3, C20, D4, D19, H9, H10, H11, H12, H13, H14, J8, J9, J10, J11, J12, J13, J14, J15, K8,
K9, K10, K11, K12, K13, K14, K15, L8, L9, L10, L11, L12, L13, L14, L15, M8, M9, M10, M11, M12, M13,
M14, M15, N8, N9, N10, N11, N12, N13, N14, N15, P8, P9, P10, P11, P12, P13, P14, P15, R9, R10, R11,
R12, R13, R14, W4, W19, Y3, Y20, AA2, AA21, AB1, AB22
VCC D6, D9, D12, D14, D17, F4, F19, G7, G8, G15, G16, H7, H16, J4, J19, L4, M19, P4, P19, R7, R16, T7, T8,
T15, T16, U4, U19, W6, W9, W11, W14, W17
VCCIO M22
NC
1
G9, G10, G11, G12, G13, G14, H8, H15, J7, J16, K7, K16, L7, L16, M7. M16, N7, N16, P7, P16, R8,
R15, T9, T10, T11, T12, T13, T14
1. NC pins are not to be connected to any active signals, VCC or GND.

ISPGDX240VA-7B388I

Mfr. #:
Manufacturer:
Lattice
Description:
Analog & Digital Crosspoint ICs PROGRAMMABLE GEN DIG CROSSPOINT
Lifecycle:
New from this manufacturer.
Delivery:
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