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LTC2631ACTS8-LM12#TRMPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
LTC2631
19
2631fc
For more information www.linear.com/LTC2631
timing Diagrams
Figure 1. Serial Interface Timing
Figure 2. Typical LTC2631 Write Transaction
SDA
t
f
S
t
r
t
LOW
t
HD(STA)
ALL VOLTAGE LEVELS REFER TO V
IH(MIN)
AND V
IL(MAX)
LEVELS
t
HD(DAT)
t
SU(DAT)
t
SU(STA)
t
HD(STA)
t
SU(STO)
t
SP
t
BUF
t
r
t
f
t
HIGH
SCL
S P S
2631 F01
ACK ACK
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
2631 F02
ACK
START
SDA
A6 A5 A4 A3
SLAVE ADDRESS
A2 A1 A0 W
SCL
C2C3 C1 C0 X X X X X X X X
ACK
1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE
LTC2631
20
2631fc
For more information www.linear.com/LTC2631
operation
The LTC2631 is a family of single voltage-output DACs
in 8-lead ThinSOT packages. Each DAC can operate rail-
to-rail using an external reference, or with its full-scale
voltage set by an integrated reference. Twelve combina
-
tions of accuracy (12-, 10-, and 8-bit), power-on reset
value (
zero or mid-scale), and full-scale voltage (2.5V or
4.096V) are available. The LTC2631 is controlled using a
2-wire I
2
C interface.
Power-On Reset
The LTC2631-HZ/LTC2631-LZ clear the output to zero-
scale when power is first applied, making system initial
-
ization consistent and repeatable.
For some
applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2631
contains circuitry to reduce the power-on glitch: the ana
-
log output
typically rises less than 5mV above zero-scale
during power
on if the power supply is ramped to 5V in
1ms or more. In general, the glitch amplitude decreases as
the power supply ramp time is increased. See “Power-On
Reset Glitch” in the Typical Performance Characteristics
section.
The LTC2631-HM/LTC2631-LM provide an alternative
reset, setting the output
to mid-scale when power is first
applied.
Default reference
mode selection is described in the Ref-
erence Modes section.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
– 0.3V ≤ V
REF
≤ V
CC
+ 0.3V (see Absolute Maximum Rat-
ings). Particular care
should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at V
CC
(Pin 5) is in transition.
Transfer Function
The digital-to-analog transfer function is
V
OUT(IDEAL)
=
k
2
N
V
REF
where k is the decimal equivalent of the binary DAC input
code, N is the resolution, and V
REF
is either 2.5V (LTC2631-
LM/LTC2631-LZ) or 4.096V (LTC2631-HM/LTC2631-HZ)
when in Internal Reference mode, and the voltage at REF
(Pin 6) when in External Reference mode.
I
2
C Serial Interface
The LTC2631 communicates with a host using the stan-
dard 2-wire I
2
C interface. The Timing Diagrams (Figures 1
and 2) show the timing
relationship of the signals on the
bus. The two bus lines, SDA and SCL, must be high when
the bus is not in use. External pull-up resistors or current
sources are required on these lines. The value of these
pull-up resistors is dependent on the power supply and
can be obtained from the I
2
C specifications. For an I
2
C
bus operating in the fast mode, an active pull-up will be
necessary if the bus capacitance is greater than 200pF.
The LTC2631 is a receive-only (slave) device. The master
can write to the LTC2631. The LTC2631 does not respond
to a read from the master.
START (S) and STOP (P) Conditions
When the bus is not
in use, both SCL and SDA must be
high. A bus master signals the beginning of a communi-
cation to
a slave device by transmitting a START condition.
A START condition is generated by transitioning SDA from
high to low while SCL is high.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another I
2
C device.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was properly received. The Acknowl
-
edge related clock pulse is generated by the master. The
master releases the SDA line (HIGH) during the Acknowl-
edge clock
pulse. The slave-receiver must pull down the
SDA bus
line during the Acknowledge clock pulse so that
it remains a stable LOW during the HIGH period of this
clock pulse. The LTC2631 responds to a write by a master
LTC2631
21
2631fc
For more information www.linear.com/LTC2631
operation
in this manner but does not acknowledge a read operation;
in that case, SDA is retained HIGH during the period of
the Acknowledge clock pulse.
Chip Address
The state of pins CA0 and CA1 (LTC2631-HZ/LTC2631-
LZ) determines the slave address of the part. These pins
can each be set to any one of three states: V
CC
, GND or
float. This results in nine (LTC2631-HZ/LTC2631-LZ) or
three (LTC2631-HM/LTC2631-LM) selectable addresses
for the part. The slave address assignments are shown
in Tables 1 and 2.
Table 1. Slave Address Map (LTC2631-Z)
CA1 CA0 A6 A5 A4 A3 A2 A1 A0
GND GND 0 0 1 0 0 0 0
GND FLOAT 0 0 1 0 0 0 1
GND V
CC
0 0 1 0 0 1 0
FLOAT GND 0 0 1 0 0 1 1
FLOAT FLOAT 0 1 0 0 0 0 0
FLOAT V
CC
0 1 0 0 0 0 1
V
CC
GND 0 1 0 0 0 1 0
V
CC
FLOAT 0 1 0 0 0 1 1
V
CC
V
CC
0 1 1 0 0 0 0
GLOBAL ADDRESS 1 1 1 0 0 1 1
Table 2. Slave Address Map (LTC2631-M)
CA0 A6 A5 A4 A3 A2 A1 A0
GND 0 0 1 0 0 0 0
FLOAT 0 0 1 0 0 0 1
V
CC
0 0 1 0 0 1 0
GLOBAL ADDRESS 1 1 1 0 0 1 1
In addition to the address selected by the address pins,
the part also responds to a global address. This address
allows a common write to all LTC2631 parts to be accom
-
plished using one 3-byte write transaction on the I
2
C bus.
The global address, listed at the end of Tables 1 and 2, is
a 7-bit hardwired address not selectable by CA0/CA1. If
another address is required, please consult the factory.
The maximum capacitive load allowed on the CA0/CA1
address pins is 10pF, as these pins are driven during ad-
dress detection to determine if they are floating.
Write Word Protocol
The master initiates communication with the LTC2631
with a START condition and a 7-bit slave address followed
by the Write bit (W) = 0. The LTC2631 acknowledges by
pulling the SDA pin low at the ninth clock if the 7-bit slave
address matches the address of the part (set by CA0/CA1)
or the global address. The master then transmits 3-bytes
of data. The LTC2631 acknowledges each
byte of data by
pulling the
SDA line low at the ninth clock of each data
byte transmission. After receiving three complete bytes
of data, the LTC2631 executes the command specified in
the 24-bit input word.
If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2631 does not acknowledge
the extra bytes of data (SDA is high during the 9th clock).
The format of the three data bytes is shown in Figure 3.
The first byte of the input word consists of the 4-bit com
-
mand, followed by four
don’t-cares bits. The next two bytes
contain the 16-bit data word, which consists of the 12-,
10- or 8-bit input code, MSB to LSB, followed by 4, 6 or 8
don’t-cares bits (LTC2631-12, LTC2631-10 and LTC2631-8
respectively). A typical LTC2631 write
transaction is
shown in Figure 4.
The command
bit assignments (C3-C0) are shown in
Table 3. The first four commands in the table consist of
write and update operations. A write operation loads a
16-bit data word from the 32-bit shift register into the
input register. In an update operation, the data word is
copied from the input register to the
DAC register and
converted to an analog voltage at the DAC output. The
update operation also powers up the DAC if it had been in
power-down mode. The data path and registers are shown
in the Block Diagram.
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LTC2631ACTS8-LM12#TRMPBF

Mfr. #:
Buy LTC2631ACTS8-LM12#TRMPBF
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 12-Bit, 1LSB INL I2C DAC (2.5V ref, Reset to Mid-Scale)
Lifecycle:
New from this manufacturer.
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