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ADP5070RE-EVALZ

P1-P3P4-P6P7-P9P10-P12P13-P13
UG-848 ADP5070RE-EVALZ/ADP5071RE-EVALZ User Guide
Rev. 0 | Page 4 of 13
Figure 3. ADP5070/ADP5071 Top Component Detail
Figure 4. Bottom of Evaluation Printed Circuit Board (PCB) Showing Locations for Optional Components
BOOST OUTPUT
CA
PACI
T
OR
(1210)
BOOST DIODE
(POWERDI123)
BOOST INDUC
TOR
(COILCRAFT XAL40xx)
INVERTER OUTPUT
CA
P
ACI
T
OR
(1210)
INVERTER INDUC
TOR
(COILCRAFT XAL40xx)
INVERTER DIODE
(POWERDI123)
INPUT CA
PACI
TOR
(1206)
ADP5070/ADP5071
(20-LEAD TSSOP)
VREG
AND VREF
INTERNAL
SUPP
LY
DECOUPLING
CA
PACI
T
ORS
(0603)
INVERTER
FEEDBACK
RESIS
TORS (0805)
RFT2 = T
OP
RFB2 = BOT
T
OM
INVERTER
COMPENSA
TION
RESIS
T
OR
AND
CA
P
ACI
T
OR (0603)
BOOST
COMPENS
A
TION
RESIS
T
OR
AND
CA
PACI
T
OR (0603)
BOOST FEEDBACK
RESIS
TORS (0805)
RFT1 =
T
OP
RFB1 = BOTT
OM
13281-003
TYPE 3
COMPENSATION
COMPONENTS
COMPENSATION MODE
CONNECT THE CENTER TERMINAL OF JP5 AND JP6 TOWARD THE
CENTER OF THE BOARD (DOTTED PIN) FOR TYPE 2 COMPENSATION.
FIT ADDITIONAL COMPONENTS AND CONNECT TOWARD THE EDGE
OF THE BOARD FOR TYPE 3.
OPTIONAL ADDITIONAL
OUTPUT CAPACITORS
13281-004
ADP5070RE-EVALZ/ADP5071RE-EVALZ User Guide UG-848
Rev. 0 | Page 5 of 13
Table 1. Evaluation Board Function Descriptions
Jumper/Connector
Mnemonic
Description
VIN Power supply to the ADP5070/ADP5071. In the default configuration, this ranges from 3 V to 5.5 V.
POS Output from boost regulator of the ADP5070/ADP5071. 15 V in default configuration.
NEG Output from inverting regulator of the ADP5070/ADP5071. −15 V in default configuration.
V_EN Provides a clamped enable voltage to allow the boards to operate using input voltages greater than 5.5 V
without damaging the EN1 and EN2 pins. For efficiency measurements, remove this jumper and provide an
enable signal from an external supply.
EN1 Boost regulator precision enable. The EN1 pin is compared to an internal precision reference to enable the
boost regulator output. Connect this jumper to the on position to turn on the boost regulator. Connect this
jumper to
the off position or remove this jumper to turn the regulator off (an internal pulldown is present in the
ADP5070/ADP5071). Connect an external enable voltage below the lesser of 5.5 V and V
IN
to the center pin
during efficiency measurement and remove the V_EN jumper.
EN2 Inverting regulator precision enable. The EN2 pin is compared to an internal precision reference to enable the
inverting regulator output. Connect this jumper to the on position to turn on the inverting regulator. Connect
this jumper to the off position or remove this jumper to turn the regulator off (an internal pulldown is present in
the ADP5070/ADP5071). Connect an external enable voltage below the lesser of 5.5 V and V
IN
to the center pin
during efficiency measurement and remove the V_EN jumper.
SYNC/FREQ Synchronization input and frequency setting. To set the switching frequency to 2.4 MHz, pull the SYNC/FREQ pin
high. To set the switching frequency to 1.2 MHz, pull the SYNC/FREQ pin low. To synchronize the switching
frequency, connect the SYNC/FREQ pin to an external clock (5.5 V maximum).
SEQ Start-up sequence control. For manual V
POS
/V
NEG
startup using an individual precision enabling pin, leave the
SEQ pin open. For simultaneous V
POS
/V
NEG
startup when the EN2 pin rises, connect the SEQ pin to VREG (use the
EN1 pin to enable internal references early, if required). For a sequenced startup, pull the SEQ pin low. Use
either EN1 or EN2 to enable V
POS
or V
NEG
and the corresponding supply is the first in sequence; hold the other
enable pin low.
SLEW
Driver stage slew rate control. The SLEW pin sets the slew rate for the SW1 and SW2 drivers. For the fastest slew
rate (best efficiency), leave the SLEW pin open. For a normal slew rate, connect the SLEW pin to VREG. For the
slowest slew rate (best noise performance), connect the SLEW pin to AGND.
SS Soft start programming. Leave the SS pin open to obtain the fastest soft start time. To program a slower soft
start time, connect this jumper. This jumper connects the RSS resistor between the SS pin and AGND.
LDO POS Positive output of the ADP7142 LDO regulator. Connect LP_VIN to use the external positive LDO regulator. Set
to 12 V in the default configuration.
LP_VIN Connects the positive output of the ADP5070/ADP5071 to the ADP7142 LDO regulator.
LP_EN Use as an external enable for the ADP7142 LDO regulator if J_LP_EN is removed.
LDO NEG Negative output of the ADP7182 LDO regulator. Connect LN_VIN to use the external negative LDO regulator.
Set to −12 V in the default configuration.
LN_VIN Connects the negative output of the ADP5070/ADP5071 to the ADP7182 LDO regulator.
LN_EN Use as an external enable for the ADP7182 LDO regulator if J_LN_EN is removed.
UG-848 ADP5070RE-EVALZ/ADP5071RE-EVALZ User Guide
Rev. 0 | Page 6 of 13
OUTPUT VOLTAGE MEASUREMENTS
For basic output voltage accuracy measurements, connect the
evaluation boards to a voltage source and a voltmeter. Use a
resistor as the load for the regulator.
Ensure that the resistor has an adequate power rating to handle
the expected power dissipation. Use an electronic load as an
alternative. Ensure that the voltage source supplies enough
current for the expected load levels, taking into account the
device efficiency.
Follow these steps to connect to a voltage source and voltmeter:
1. Connect the negative (−) terminal of the voltage source
to the GND terminal of the power input connector on the
right side of the evaluation boards.
2. Connect the positive (+) terminal of the voltage source
to the VIN terminal of the power input connector on the
right side of the evaluation boards.
3. Connect a load between the POS or NEG terminal and
GND terminal at the output connector (center top of the
PCB).
4. Connect the voltmeter across the selected output terminal
and ground in parallel with the load resistor.
Turn the voltage source on. If the EN1 or EN2 jumper is in the
on position, the respective boost or inverting regulator powers
up. Disconnect the SEQ jumper.
If the load current is large, the user must connect the voltmeter as
close as possible to the output capacitor to reduce the effects of
voltage drops due to PCB trace impedance.
If long power leads are used from the power supply, especially
at higher loads, connect a large capacitor (10,000 μF or more)
across the VIN terminals to prevent losses from lead inductance.
Measure the input voltage at these terminals or use a power
supply with a 4-wire supply and sense arrangement.
LINE REGULATION
For line regulation measurements, monitor the regulator
output while its input is varied. For good line regulation, the
output must change as little as possible with varying input
levels. It is possible to repeat this measurement under different
load conditions. During line regulation tests, keep the power
supply leads short and remove any additional input capacitor.
Figure 5 and Figure 6 show the typical line regulation performance
of the ADP5070/ADP5071 at both the output and feedback pins.
Figure 5. Boost Regulator Line Regulation, V
POS
= 15 V, f
SW
= 1.2 MHz, 15 mA
Load, T
A
= 25°C (Nominal Defined as Average Value Within a Range of 10%
to 90% V
IN
)
Figure 6. Inverting Regulator Line Regulation, V
NEG
= −15 V, f
SW
= 1.2 MHz,
15 mA Load, T
A
= 25°C (Nominal Defined as Average Value Within a Range of
10% to 90% V
IN
)
–0.5
–0.3
–0.1
0.1
0.3
0.5
V
IN
(V)
0 5 10 15 20
VARIATION FROM NOMINAL (%)
V
OUT
ACCURACY
V
REF
ACCURACY
FBx VOLTAGE ACCURACY
13281-006
P1-P3P4-P6P7-P9P10-P12P13-P13

ADP5070RE-EVALZ

Mfr. #:
Buy ADP5070RE-EVALZ
Manufacturer:
Analog Devices / Linear Technology
Description:
Power Management IC Development Tools Dual Switching Reg for Vpos & Vneg
Lifecycle:
New from this manufacturer.
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