Data Sheet 14 Rev. 1.1, 2004-01-01
TLE 4299
Reset
The power on reset feature is necessary for a defined start of the microprocessor when
switching on the application. For the reset delay time after the output voltage of the
regulator is above the reset threshold, the reset signal is set High again. The reset delay
time is defined by the reset delay capacitor
C
D
at pin D.
The under-voltage reset circuitry supervises the output voltage. In case
V
Q
decreases
below the reset threshold the reset output is set LOW after the reset reaction time. The
reset LOW signal is generated down to an output voltage
V
Q
to 1 V. Both the reset
reaction time and the reset delay time is defined by the capacitor value.
The power on reset delay time is defined by the charging time of an external delay
capacitor
C
D
.
C
D
= (t
d
× I
D
) / ∆V (1)
Definitions:
•
C
D
= reset delay capacitor
•
t
d
= reset delay time
•
∆V = V
UD
, typical 1.8 V for power up reset
•
∆V = V
UD
- V
LD
, typical 1.35 V for undervoltage reset
•
I
D
= charge current, typical 6.5 µA
For a delay capacitor
C
D
= 100 nF the typical power on reset delay time is 28 ms.
The reset reaction time
t
RR
is the time it takes the voltage regulator to set reset output
LOW after the output voltage has dropped below the reset threshold. It is typically 1
µs
for delay capacitor of 100 nF. For other values for
C
D
the reaction time can be estimated
using the following equation:
t
RR
= 10 ns / nF × C
D
(2)
