MC14174BDR2

MC14174B
http://onsemi.com
4
SWITCHING CHARACTERISTICS
(7.)
(C
L
= 50 pF, T
A
= 25C)
V
DD
All Types
Characteristic Symbol
V
DD
Vdc Min Typ
(8.)
Max
Unit
Output Rise and Fall Time
t
TLH
, t
THL
= (1.35 ns/pF) C
L
+ 32 ns
t
TLH
, t
THL
= (0.6 ns/pF) C
L
+ 20 ns
t
TLH
, t
THL
= (0.4 ns/pF) C
L
+ 20 ns
t
TLH
, t
THL
5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay Time — Clock to Q
t
PLH
, t
PHL
= (0.9 ns/pF) C
L
+ 165 ns
t
PLH
, t
PHL
= (0.36 ns/pF) C
L
+ 64 ns
t
PLH
, t
PHL
= (0.26 ns/pF) C
L
+ 52 ns
t
PLH
, t
PHL
5.0
10
15
210
85
65
400
160
120
ns
Propagation Delay Time — Reset to Q
t
PHL
= (0.9 ns/pF) C
L
+ 205 ns
t
PHL
= (0.36 ns/pF) C
L
+ 79 ns
t
PHL
= (0.26 ns/pF) C
L
+ 62 ns
t
PHL
5.0
10
15
250
100
75
500
200
150
ns
Clock Pulse Width t
WH
5.0
10
15
150
90
70
75
45
35
ns
Reset Pulse Width t
WL
5.0
10
15
200
100
80
100
50
40
ns
Clock Pulse Frequency f
cl
5.0
10
15
7.0
12
15.5
2.0
5.0
6.5
mHz
Clock Pulse Rise and Fall Time t
TLH
, t
THL
5.0
10
15
15
5.0
4.0
s
Data Setup Time t
su
5.0
10
15
40
20
15
20
10
0
ns
Data Hold Time t
h
5.0
10
15
80
40
30
40
20
15
ns
Reset Removal Time t
rem
5.0
10
15
250
100
80
125
50
40
ns
7. The formulas given are for the typical characteristics only at 25C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MC14174B
http://onsemi.com
5
FUNCTIONAL BLOCK DIAGRAM
TIMING DIAGRAM
MC14174B
http://onsemi.com
6
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
R
X 45
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019


MC14174BDR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Flip Flops 3-18V CMOS Hex
Lifecycle:
New from this manufacturer.
Delivery:
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