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AD7878LPZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
AD7878
–3–
REV. A
Limit at T
MIN
, T
MAX
Limit at T
MIN
, T
MAX
Limit at T
MIN
, T
MAX
Parameter (L Grade) (J, K, A, B Grades) (S Grade) Units Conditions/Comments
t
l
65 65 75 ns max CLK IN to BUSY Low Propagation Delay
t
2
65 65 75 ns max CLK IN to BUSY High Propagation Delay
t
3
2 CLK IN Cycles 2 CLK IN Cycles 2 CLK IN Cycles min CONVST Pulse Width
t
4
0 0 0 ns min CS to DMRD/REGISTER ENABLE Setup Time
t
5
0 0 0 ns min CS to DMRD/ REGISTER ENABLE Hold Time
t
6
45 60 60 ns min DMRD Pulse Width
50 50 50 µs max
t
7
16 16 16 ns min ADD0 to DMRD/REGISTER ENABLE Setup Time
t
8
0 0 0 ns min ADD0 to DMRD/REGISTER ENABLE Hold Time
t
9
2
41 57 57 ns min Data Access Time after DMRD
t
10
3
5 5 5 ns min Bus Relinquish Time
45 45 45 ns max
t
11
42 42 55 ns min REGISTER ENABLE Pulse Width
50 50 50 µs max
t
12
20 20 30 ns min Data Valid to REGISTER ENABLE Setup Time
t
13
10 10 10 ns min Data Hold Time after REGISTER ENABLE
t
14
2
41 57 57 ns min Data Access Time after BUSY
t
RESET
2 CLK IN Cycles 2 CLK IN Cycles 2 CLK IN Cycles min RESET Pulse Width
NOTES
1
Timing Specifications in bold print are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
t
9
and t
14
are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3
t
10
is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
(V
DD
= 5 V 6 5%, V
CC
= 5 V 6 5%, V
SS
= –5 V 6 5%)
TIMING CHARACTERISTICS
1
Figure 1. Load Circuits for Access Time
Figure 2. Load Circuits for Output Float Delay
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise stated)
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
CC
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
SS
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
V
DD
to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+0.3 V
V
IN
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V
DD
Digital Inputs to DGND
CLK IN, DMWR, DMRD, RESET,
CS, CONVST, ADD0 . . . . . . . . . . . . –0.3 V to V
DD
+0.3 V
Di
gital Outputs to DGND
ALFL, BUSY . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+0.3 V
Data Pins
DB11–DB0 . . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+0.3 V
Operating Temperature Range
J, K, L Versions . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
S Version . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
Power Dissipation (Any Package) to +75°C . . . . . . 1000 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . 10 mW/°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7878 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
a. High-Z to V
OH
b. High-Z to V
OL
a. V
OH
to High-Z
b. V
OL
to High-Z
AD7878
–4–
REV. A
PIN FUNCTION DESCRIPTION
Pin Pin
Number Mnemonic Function
11 ADD0 Address Input. This control input determines whether the word placed on the output data bus during a read operation is a data
word from the FIFO RAM or the contents of the status/control register. A logic low accesses the data word from Location 0 of
the FIFO while a logic high selects the contents of the register (see Status/Control Register section).
12 CS Chip Select. Active low logic input. The device is selected when this input is active.
13 DMWR Dam Memory Write. Active low logic input. DMWR is used in conjunction with CS low and ADD0 high to write data to the
status/control register. Corresponds to DMWR (ADSP-2100), R/W (MC68000, TMS32020), WE (TMS32010).
14 DMRD Data Memory READ. Active low logic input. DMRD is used in conjunction with CS low to enable the three-state output buffers.
Corresponds directly to DMRD (ADSP-2100), DEN (TMS32010).
15 BUSY Active Low Logic Output. This output goes low when the ADC receives a CONVST pulse and remains low until the track/hold
has gone into its hold mode. The three-state drivers of the AD7878 can be disabled while the BUSY signal is low (see Extended
READ/WRITE section). This is achieved by writing a logic 0 to DB5 (DISO) of the status/control register. Writing a logic 1 to
DB5 of the status/control register allows data to be accessed from the AD7878 while BUSY is low.
16 ALFL FIFO Almost Full. A logic low indicates that the word count (i.e., number of conversion results) in the FIFO memory has
reached the programmed word count in the status/control register. ALFL is updated at the end of each conversion. The ALFL
output is reset to a logic high when a word is read from the FIFO memory and the word count is less than the preprogrammed
word count. It can also be set high by writing a logic 1 to DB7 (ENAF) of the status/control register.
17 DGND Digital Ground. Ground reference for digital circuitry.
18V
CC
Digital supply voltage, +5 V ± 5%. Positive supply voltage for digital circuitry.
19 DB11 Data Bit 11 (MSB). Three-state TTL output. Coding for the data words in FIFO RAM is twos complement.
10–15 DB10–DB5 Data Bit 10 to Data Bit 5. Three-state TTL input/outputs.
16–19 DB4–DB1 Data Bit 4 to Data Bit 1. Three-state TTL outputs.
20 DB0 Data Bit 0 (LSB). Three-state TTL output.
21 V
DD
Analog positive supply voltage, +5 V ± 5%.
22 AGND Analog Ground. Ground reference for track/hold, reference and DAC.
23 REF OUT Voltage Reference Output. The internal 3 V analog reference is provided at this pin. The external load capability of the reference
is 500 µA.
24 V
IN
Analog Input. Analog input range is ±3 V.
25 V
SS
Analog negative supply voltage, –5 V ± 5%.
26 CONVST Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold mode and starts conversion.
The CONVST input is asynchronous to CLK IN and independent of CS, DMWR and DMRD.
27 RESET Reset. Active low logic input. A logic low sets the words in FIFO memory to 1000 0000 0000 and resets the ALFL output and
status/control register.
28 CLK IN Clock Input. TTL-compatible logic input. Used as the clock source for the A/D converter. The mark-space ratio of this clock can
vary from 35/65 to 65/35.
PIN CONFIGURATIONS
LCCC
PLCC
DIP
AD7878
–5–
REV. A
ORDERING GUIDE
Signal- Data
Temperature to-Noise Access Package
Model
1, 2
Range Ratio Time Options
3
AD7878JN 0°C to +70°C 70 dB 57 ns N-28
AD7878AQ –25°C to +85°C 70 dB 57 ns Q-28
AD7878SQ –55°C to +125°C 70 dB 57 ns Q-28
AD7878KN 0°C to +70°C 72 dB 57 ns N-28
AD7878BQ –25°C to +85°C 72 dB 57 ns Q-28
AD7878LN 0°C to +70°C 72 dB 41 ns N-28
AD7878SE
4
–55°C to +125°C 70 dB 57 ns E-28A
AD7878JP 0°C to +70°C 70 dB 57 ns P-28A
AD7878KP 0°C to +70°C 72 dB 57 ns P-28A
AD7878LP 0°C to +70°C 72 dB 41 ns P-28A
NOTES
1
To order MIL-STD-883, Class B processed parts, add /883B to part number.
Contact our local sales office for military data sheet.
2
Analog Devices reserves the right to ship either ceramic (D-28) packages or
cerdip (Q-28) hermetic packages.
3
E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier, Q = Cerdip.
4
Available to /883B processing only.
STATUS/CONTROL REGISTER
The status/control register serves the dual function of providing
control and monitoring the status of the FIFO memory. This
register is directly accessible through the data bus (DB11–DB0)
with a read or write operation while ADD0 is high. A write
operation to the status/control register provides control for the
ALFL output, bus interface and FIFO counter reset. This is
normally done on power-up initialization. The FIFO memory
address pointer is incremented after each conversion and com-
pared with a preprogrammed count in the status/control regis-
ter. When this preprogrammed count is reached, the ALFL
output is asserted if the ENAF control bit is set to zero. This
ALFL can be used to interrupt the microprocessor after any
predetermined number of conversions (between 1 and 8). The
status of the address pointer along with sample overrange and
ALFL status can be accessed at any time by reading the status/
control register. Note: reading the status/control register does
not cause any internal data movement in the FIFO memory.
Status information for a particular word should be read from the
status register before the data word is read from the FIFO
memory.
STATUS/CONTROL REGISTER FUNCTION
DESCRIPTION
DB11 (ALFL)
Almost Full Flag, Read only. This is the same as Pin 6 (ALFL
output) status. A logic low indicates that the word count in
the FIFO memory has reached the preprogrammed count in bit
locations DB10–DB8. ALFL is updated at the end of conversion.
DB10–DB8 (AFC2–AFC0)
Almost Full Word Count, Read/Write. The count value deter-
mines the number of words in the FIFO memory, which will
cause ALFL to be set. When the FIFO word count equals the
programmed count in these three bits, both the ALFL output
and DB11 of the status register are set to a logic low. For ex-
ample, when a code of 011 is written to these bits, ALFL is set
when Location 0 through Location 3 of the FIFO memory
contains valid data. AFC2 is the most significant bit of the word
count. The count value can be read back if required.
DB7 (ENAF)
Enable Almost Full, Read/Write. Writing a 1 to this bit disables
the ALFL output and status register bit DB11.
DB6 (FOVR/RESET)
FIFO Overrun/RESET, Read/Write. Reading a 1 from this bit
indicates that at least one sample has been discarded because
the FIFO memory is full. When the FIFO is full (i.e., contains
eight words) any further conversion results will be lost. Writing
a 1 to this bit causes a system RESET as per the RESET input
(Pin 27).
DB5 (FOOR/DISO)
FIFO Out of RANGE/Disable Outputs, Read/Write. Reading a
1 from this bit indicates that at least one sample in the FIFO
memory is out of range. Writing a 0 to this bit prevents the data
bus from becoming active while BUSY is low, regardless of the
state of CS and DMRD.
DB4 (FEMP)
FIFO Empty, Read Only. Reading a 1 indicates there are no
samples in the FIFO memory. When the FIFO is empty the
internal ripple-down effects of the FIFO are disabled and fur-
ther reads will continue to access the last valid data word in
Location 0.
DB3 (SOOR)
Sample out of Range, Read Only. Reading a 1 indicates the next
sample to be read is out of range, i.e., the sample in Location 0
of the FIFO.
DB–DB0 (FCN2–FCN0)
FIFO Word Count, Read Only. The value read from these bits
indicates the number of samples in the FIFO memory. For
example, reading 011 from these bits indicates that Location 0
through Location 3 contains valid data. Note: reading all 0s
indicates there is either one word or no word in the FIFO
memory; in this case the FIFO Empty determines if there is no
word in memory. FCN2 is the most significant bit.
Table I. Status/Control Bit Function Description
BIT LOCATION DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
STATUS INFORMATION (READ) ALFL AFC2 AFC1 AFC0 ENAF FOVR FOOR FEMP SOOR FCN2 FCN1 FCN0
CONTROL FUNCTION (WRITE) X AFC2 AFC1 AFC0 ENAF RESET DISO XXXXX
RESET STATUS 1 0 0 0 0 0 0 1 0 0 0 0
X =DON’T CARE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD7878LPZ-REEL

Mfr. #:
Buy AD7878LPZ-REEL
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC CMOS Complete 12-Bit 100kHz Sampling
Lifecycle:
New from this manufacturer.
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