AD7878LPZ-REEL Datasheet AD7878SQ, AD7878BQ, AD7878JNZ | P7-P9

AD7878

–6–

REV. A

INTERNAL FIFO MEMORY

The internal FIFO memory of the AD7878 consists of eight

memory locations. Each word in memory contains 13 bits of

information—12 bits of data from the conversion result and one

additional bit which contains information as to whether the 12-

bit result is out of range or not. A block diagram of the AD7878

FIFO architecture is shown in Figure 3.

Figure 3. Internal FIFO Architecture

The conversion result is gathered in the successive approxima-

tion register (SAR) during conversion. At the end of conversion

this result is transferred to the FIFO memory. The FIFO ad-

dress pointer always points to the top of memory, which is the

uppermost location containing valid data. The pointer is incre-

mented after each conversion. A read operation from the FIFO

memory accesses data from the bottom of the FIFO, Location 0.

On completion of the read operation, each data word moves

down one location and the address pointer is decremented by

one. Therefore, each conversion result from the SAR enters at

the top of memory, propagates down with successive reads until

it reaches Location 0 from where it can be accessed by a micro-

processor read operation.

The transfer of information from the SAR to the FIFO occurs in

synchronization with the AD7878 input clock (CLK IN). The

propagation of data words down the FIFO is also synchronous

with this clock. As a result, a read operation to obtain data from

the FIFO must also be synchronous with CLK IN to avoid

Read/Write conflicts in the FIFO (i.e., reading from FIFO Loca-

tion 0 while it is being updated). This requires that the micro-

processor clock and the AD7878 CLK IN are derived from the

same source.

INTERNAL COMPARATOR TIMING

The ADC clock, which is applied to CLK IN, controls the suc-

cessive approximation A/D conversion process. This clock is

internally divided by four to yield a bit trial cycle time of 500 ns

min (CLK IN = 8 MHz clock). Each bit decision occurs 25 ns

after the rising edge of this divided clock. The bit decision is

latched by the rising edge of an internal comparator strobe sig-

nal. There are 12-bit decisions, as in a normal successive ap-

proximation routine, and one extra decision that checks if the

input sample is out of range. In a normal successive approxima-

tion A/D converter, reading data from the device during conver-

sion can upset the conversion in progress. This is due to on-chip

transients, generated by charging or discharging the databus,

concurrent with a bit decision. The scheme outlined below and

shown in Figure 4 describes how the AD7878 overcomes this

problem.

The internal comparator strobe on the AD7878 is gated with

both DMRD and DMWR so that if a read or write operation

occurs when a bit decision is about to be made, the bit decision

point is deferred by one CLK IN cycle. In other words, if

DMRD or DMWR goes low (with CS low) at any time during

the CLK IN low time immediately prior to the comparator

strobing edge (t

LOW

of Figure 4), the bit trial is suspended for a

clock cycle. This makes sure that the bit decision is latched at a

time when the AD7878 is not attempting to charge or discharge

the data bus, thereby ensuring that no spurious transients occur

internally near a bit decision point.

The decision point slippage mechanism is shown in Figure 4 for

the MSB decision. Normally, the MSB decision occurs 25 ns

after the fourth rising CLK IN edge after CONVST goes high.

However, in the timing diagram of Figure 4, CS and DMRD or

DMWR are low in the time period t

LOW

prior to the MSB deci-

sion point on the fourth rising edge. This causes the internal

comparator strobe to be slipped to the fifth rising clock edge.

The AD7878 will again check during a period t

LOW

prior to this

fifth rising clock edge; and if the CS and DMRD or DMWR are

still low, the bit decision point will be slipped a further clock

cycle.

The conversion time for the ADC normally consists of the 13-

bit trials described above and one extra internal clock cycle during

which data is written from the SAR to the FIFO. For an 8 MHz

input clock this results in a conversion time of 7 µs. However,

the software routine servicing the AD7878 has the potential to

read 16 times from the device during conversion—8 reads from

the FIFO and 8 reads from the status/control register. It also has

the potential to write once to the status/control register. If these

Figure 4. Operational Timing Diagram

AD7878

–7–

REV. A

17 (16 read plus 1 write) operations all occur during t

LOW

time

periods, the conversion time will slip by 17 CLK IN cycles.

Therefore, if read or write operations can occur during t

LOW

periods, it means that the conversion time for the ADC can vary

from 7 µs to 9.12 µs (assuming 8 MHz CLK IN). This calcula-

tion assumes there is a slippage of one CLK IN cycle for each

read or write operation.

INITIATING A CONVERSION

Conversion is initiated on the AD7878 by asserting the CONVST

input. This CONVST input is an asynchronous input indepen-

dent of either the ADC or DSP clocks. This is essential for applica-

tions where precise sampling in time is important. In these applica-

tions the signal sampling must occur at exactly equal intervals to

minimize errors due to sampling uncertainty or jitter. In these cases

the CONVST input is driven from a tamer or some precise clock

source. On receipt of a CONVST pulse, the AD7878 acknowl-

edges by taking the BUSY output low. This BUSY output can be

used to ensure no bus activity while the track/hold goes from track

to hold mode (see Extended Read/Write section). The CONVST

input must stay low for at least two CLK IN periods. The track/

hold amplifier switches from the track to hold mode on the rising

edge of CONVST and conversion is also initiated at this point.

The BUSY output returns high after the CONVST input goes high

and the ADC begins its successive approximation routine. Once

conversion has been initiated another conversion start should not

be attempted until the full conversion cycle has been completed.

Figure 5 shows the taming diagram for the conversion start.

In applications where precise sampling is not critical, the

CONVST pulse can be generated from a microprocessor WR

or RD line gated with a decoded address (different from the

AD7878 CS address). Note that the CONVST pulse width

must be a minimum of two AD7878 CLK IN cycles.

Figure 5. Conversion Start Timing Diagram

READ/WRITE OPERATIONS

The AD7878 read/write operations consist of reading from the

FIFO memory and reading and writing from the status/control

DMWR and ADD0 logic inputs. A description of these operations

is given in the following sections. In addition to the basic read/write

operations there is an extended read/write operation. This can

occur if a read/write operation occurs during a CONVST pulse.

This extended read/write is intended for use with microproces-

sors that can be driven into a WAIT state, and the scheme is

recommended for applications where an external timer controls

the CONVST input asynchronously to the microprocessor read/

write operations.

Basic Read Operation

Figure 6 shows the timing diagram for a basic read operation on

the AD7878. CS and DMRD going low accesses data from

either the status/control register or the FIFO memory. A read

operation with ADD0 low accesses data from the FIFO while a

read with ADD0 high accesses data from the status/ control

Figure 6. Basic Read Operation

Basic Write Operation

A basic write operation to the AD7878 status/control register

consists of bringing CS and DMWR low with ADD0 high. In-

ternally these signals are gated with CLK IN to provide an

internal REGISTER ENABLE signal (see Figure 7). The pulse

width of this REGISTER ENABLE signal is effectively the

overlap between the CLK IN low time and the DMWR pulse.

This may result in shorter write pulse widths, data setup times

and data hold times than those given by the microprocessor.

The timing on the AD7878 timing diagram of Figure 8 is there-

fore given with respect to the internal REGISTER ENABLE

signal rather than the DMWR signal.

Figure 7.

DMWR

Internal Logic

Figure 8. Basic Write Operation

AD7878

–8–

REV. A

Extended Read/Write Operation

As described earlier, a read/write operation to the AD7878 can

cause spurious on-chip transients. Should these transients occur

while the track/hold is going from track to hold mode, it may

result in an incorrect value of V

being held by the track/hold

amplifier. Because the CONVST input has asynchronous capa-

bility, a read/write operation could occur while CONVST is

low. The AD7878 allows the read/write operation to occur but

has the facility to disable its three-state drivers so that there is

no data bus activity and, hence, no transients while the track/

hold goes from track to hold.

Writing a logic 0 to DB5 (DISO) of the status/control register

prevents the output latches from being enabled while the

AD7878 BUSY signal is low. If a microprocessor read/write

operation can occur during the BUSY low time, the BUSY

should be gated with CS of the AD7878 and this gated signal

used to stretch the instruction cycle using DMACK (ADSP-

2100), READY (TMS32020) or DTACK (68000).

When CONVST goes low, the AD7878 acknowledges it by

bringing BUSY low on the next rising edge of CLK IN. With a

logic 0 in DB5, the AD7878 data bus cannot now be enabled. If

a read/write operation now occurs, the BUSY and CS gated

signal drives the microprocessor into a WAIT state, thereby

extending the read/write operation. BUSY goes high on the

second rising edge of CLK IN after CONVST goes high. The

AD7878 data outputs are now enabled and the microprocessor

is released from its WAIT state, allowing it to complete its read/

write operation to the AD7878.

The microprocessor cycle time for the read/write operation is

extended by the CONVST pulse width plus two CLK IN peri-

ods worst case. This is the maximum length of time for which

BUSY can be low. Assuming a CONVST pulse width of two

CLK IN periods and an 8 MHz CLK IN, the instruction cycle

is extended by 500 ns maximum. Figure 9 shows the timing

diagram for an extended read operation. In a similar manner, a

write operation will be extended if it occurs during a CONVST

pulse.

For processors that cannot be forced into a WAIT state, writing

a logic 1 into DB5 of the status/control register allows the out-

put latches to be enabled while BUSY is low. In this case BUSY

still goes low as before, but it would not be used to stretch the

read/write cycle and the instruction cycle continues as normal

(see Figures 6 and 8).

Figure 9. Extended Read Operation

AD7878 DYNAMIC SPECIFICATIONS

The AD7878 is specified and 100% tested for dynamic perfor-

mance specifications rather than for traditional dc specifications

such as Integral and Differential Nonlinearity. These ac specifi-

cations provide information on the AD7878’s effect on the spec-

tral content of the input signal. Hence, the parameters for which

the AD7878 is specified include SNR, Harmonic Distortion, inter-

modulation Distortion and Peak Harmonics. These terms are dis-

cussed in more detail in the following sections.

Signal-to-Noise Ratio (SNR)

SNR is the measured signal-to-noise ratio at the output of the

ADC. The signal is the rms magnitude of the fundamental.

Noise is the rms sum of all the nonfundamental signals (excluding

dc) up to half the sampling frequency (f

/2). SNR is dependent

upon the number of quantization levels used in the digitization

process; the more levels, the smaller the quantization noise. The

theoretical signal-to-noise ratio for a sine wave input is given by

SNR = (6.02 N + 1.76) dB (1)

where N is the number of bits. Thus for an ideal 12-bit con-

verter, SNR = 74 dB.

The output spectrum from the ADC is evaluated by applying a

sine-wave signal of very low distortion to the V

input, which is

sampled at a 100 kHz sampling rate. A Fast Fourier Transform

(FFT) plot is generated from which the SNR data can be ob-

tained. Figure 10 shows a typical 2048 point FFT plot of the

AD7878KN with an input signal of 25 kHz and a sampling

frequency of 100 kHz. The SNR obtained from this graph is

72.6 dB. It should be noted that the harmonics are included in

the SNR calculation.

Figure 10. AD7878 FFT Plot

Effective Number of Bits

The formula given in (1) relates the SNR to the number of bits.

Rewriting the formula, as in (2), it is possible to get a measure of

performance expressed in effective number of bits (N). The

effective number of bits for a device can be calculated directly

from its measured SNR.

N =

SNR –1.76

6.02

(2)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

AD7878LPZ-REEL

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Analog to Digital Converters - ADC CMOS Complete 12-Bit 100kHz Sampling

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AD7878LPZ-REEL

AD7878LPZ-REEL

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