844031BGI-01LF Datasheet 844031BGI-01LFT, 844031BGI-01LF, 844031BGI-01 | P7-P9

REVISION A 6/2/16

844031I-01 DATA SHEET

7 FEMTOCLOCKS™ CRYSTAL-TO-LVDS

CLOCK GENERATOR

APPLICATION INFORMATION

FIGURE 2. CRYSTAL INPUt INTERFACE

CRYSTAL INPUT INTERFACE

The 844031I-01 has been characterized with 18pF parallel

resonant crystals. The capacitor values, C1 and C2, shown in

Figure 2 below were determined using a 25MHz, 18pF parallel

resonant crystal and were chosen to minimize the ppm error.

The optimum C1 and C2 values can be slightly adjusted for different

board layouts.

POWER SUPPLY FILTERING TECHNIQUES

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter performance,

power supply isolation is required. The 844031I-01 provides sep-

arate power supplies to isolate any high switching noise from the

outputs to the internal PLL. V

and V

DDA

should be individually

connected to the power supply plane through vias, and 0.01µF

bypass capacitors should be used for each pin. Figure 1 illustrates

this for a generic V

pin and also shows that V

DDA

requires that

an additional10Ω resistor along with a 10µF bypass capacitor be

connected to the V

DDA

pin.

FIGURE 1. POWER SUPPLY FILTERING

10Ω

DDA

10μF

.01μF

3.3V or 2.5V

.01μF

FEMTOCLOCKS™ CRYSTAL-TO-LVDS

CLOCK GENERATOR

844031I-01 DATA SHEET

8 REVISION A 6/2/16

3.3V, 2.5V LVDS DRIVER TERMINATION

A general LVDS interface is shown in Figure 4 In a 100Ω

differential transmission line environment, LVDS drivers

require a matched load termination of 100Ω across near

FIGURE 4. TYPICAL LVDS DRIVER T ERMINATION

the receiver input. For a multiple LVDS outputs buffer, if only

partial outputs are used, it is recommended to terminate the

unused outputs.

REVISION A 6/2/16

844031I-01 DATA SHEET

9 FEMTOCLOCKS™ CRYSTAL-TO-LVDS

CLOCK GENERATOR

FIGURE 5A. APPLICATION SCHEMATIC EXAMPLE

APPLICATION SCHEMATIC

Figure 5A provides a schematic example of 844031I-01. In

this example, an 18 pF parallel resonant crystal is used. The

C1 = 22pF and C2 = 22pF are recommended for frequency.

The C1 and C2 values may be slightly adjusted for optimizing

frequency accuracy. At least one decoupling capacitor near

the power pin is required. Suggested value range is from

0.01µF to 0.1µF. Other ﬁ lter type can be added depending on

the system power supply noise type.

FIGURE 5B. 844031I-01 PC BOARD LAYOUT EXAMPLE

PC BOARD LAYOUT EXAMPLE

Figure 5B shows an example of 844031I-01 P.C. board layout. The

crystal X1 footprint shown in this example allows installation of

either surface mount HC49S or through-hole HC49 package. The

footprints of other components in this example are listed in the Ta bl e

6. There should be at least one decoupling capacitor per power pin.

The decoupling capacitors should be located as close as possible

to the power pins. The layout assumes that the board has clean

analog power ground plane.

TABLE 6. FOOTPRINT TABLE

Reference Size

C1, C2 0402

C3 0805

C4, C5 0603

R2 0603

NOTE: Table 6, lists component sizes

shown in this layout example.

VDDA

VDD

33pF

0.01u

0.1u

Zo = 50 Ohm

LVDS

Zo = 50 Ohm

VDD= 3.3V or 2.5V

ICS844031i-01

VCCA

GND

XTAL_OUT

XTAL_IN

VDD

nQ0

CL=18pF

100

10uF

27pF

P1-P3 P4-P6 P7-P9 P10-P12 P13-P14

844031BGI-01LF

Mfr. #:

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844031BGI-01LF

844031BGI-01LF

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