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ADF4002SRU-EP

P1-P3P4-P6P7-P8
Phase Detector/Frequency Synthesizer
ADF4002-EP
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.
FEATURES
400 MHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (V
P
) allows extended
tuning voltage in 3 V systems
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
104 MHz phase frequency detector
Supports defense and aerospace applications
(AQEC standard)
Military temperature range: −55°C to +125°C
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available on request
APPLICATIONS
Clock conditioning
Clock generation
IF LO generation
GENERAL DESCRIPTION
The ADF4002-EP frequency synthesizer is used to implement
local oscillators in the upconversion and downconversion sections
of wireless receivers and transmitters. It consists of a low noise
digital phase frequency detector (PFD), a precision charge pump,
a programmable reference divider, and a programmable N divider.
The 14-bit reference counter (R counter) allows selectable REF
IN
frequencies at the PFD input. A complete phase-locked loop (PLL)
can be implemented if the synthesizer is used with an external
loop filter and voltage controlled oscillator (VCO). In addition,
by programming R and N to 1, the part can be used as a stand-
alone PFD and charge pump.
Additional application and technical information can be found
in the ADF4002 data sheet.
FUNCTIONAL BLOCK DIAGRAM
CLK
DATA
LE
REF
IN
RF
IN
A
RF
IN
B
24-BIT INPUT
REGISTER
SD
OUT
A
V
DD
DV
DD
CE
AGND
DGND
14-BIT
R COUNTER
R COUNTER
LATCH
22
14
FUNCTION
LATCH
N COUNTER
LATCH
13-BIT
N COUNTER
M3 M2 M1
MUX
SD
OUT
AV
DD
HIGH-Z
MUXOUT
CPGND
R
SET
V
P
CP
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
REFERENCE
CHARGE
PUMP
CURRENT
SETTING 1
ADF4002-EP
CPI3 CPI2 CPI1
CPI6 CPI5 CPI4
CURRENT
SETTING 2
09187-001
Figure 1.
ADF4002-EP
Rev. 0 | Page 2 of 8
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings ............................................................5
Thermal Characteristics ...............................................................5
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions ..............................6
Typical Performance Characteristics ..............................................7
Outline Dimensions ..........................................................................8
Ordering Guide .............................................................................8
REVISION HISTORY
11/10—Revision 0: Initial Version
ADF4002-EP
Rev. 0 | Page 3 of 8
SPECIFICATIONS
AV
DD
= DV
DD
= 3 V ± 10%, AV
DD
≤ V
P
≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
SET
= 5.1 kΩ, dBm referred to 50 Ω, T
A
= T
MAX
to T
MIN
,
unless otherwise noted. Operating temperature range is −55°C to +125°C.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
RF CHARACTERISTICS
RF Input Sensitivity −10 0 dBm
RF Input Frequency (RF
IN
) 5 400 MHz For RF
IN
< 5 MHz, ensure slew rate (SR) > 4 V/μs
REF
IN
CHARACTERISTICS
REF
IN
Input Frequency 20 300 MHz For REF
IN
< 20 MHz, ensure SR > 50 V/μs
REF
IN
Input Sensitivity
1
0.8 AV
DD
V p-p Biased at AV
DD
/2 (ac coupling ensures AV
DD
/2 bias)
REF
IN
Input Capacitance 10 pF
REF
IN
Input Current ±100 μA
PHASE FREQUENCY DETECTOR (PFD)
Phase Detector Frequency
2
104 MHz ABP[2:1] = 00 (2.9 ns antibacklash pulse width)
CHARGE PUMP Programmable
I
CP
Sink/Source
High Value 5 mA R
SET
= 5.1 kΩ
Low Value 625 μA
Absolute Accuracy 2.5 % R
SET
= 5.1 kΩ
R
SET
Range 3.0 11 kΩ
I
CP
Three-State Leakage 1 nA T
A
= 25°C
I
CP
vs. V
CP
1.5 % 0.5 V ≤ V
CP
≤ (V
P
− 0.5 V)
Sink and Source Current Matching 2 % 0.5 V ≤ V
CP
≤ (V
P
− 0.5 V)
I
CP
vs. Temperature 2 % V
CP
= V
P
/2
LOGIC INPUTS
Input High Voltage, V
IH
1.4 V
Input Low Voltage, V
IL
0.6 V
Input Current, I
INH
, I
INL
±1 μA
Input Capacitance, C
IN
10 pF
LOGIC OUTPUTS
Output High Voltage, V
OH
1.4 V Open-drain output, 1 kΩ pull-up resistor to 1.8 V
DV
DD
− 0.4 V CMOS output
Output High Current, I
OH
100 μA
Output Low Voltage, V
OL
0.4 V I
OL
= 500 μA
POWER SUPPLIES
AV
DD
2.7 3.3 V
DV
DD
AV
DD
V
V
P
AV
DD
5.5 V AV
DD
≤ V
P
≤ 5.5 V
I
DD
3
(AI
DD
+ DI
DD
) 5.0 6.0 mA
I
P
0.4 mA T
A
= 25°C
Power-Down Mode 1 μA AI
DD
+ DI
DD
NOISE CHARACTERISTICS
Normalized Phase Noise Floor (PN
SYNTH
)
4, 5
−222 dBc/Hz PLL loop bandwidth = 500 kHz
Normalized 1/f Noise (PN
1_f
)
4, 6
−119 dBc/Hz Measured at 10 kHz offset; normalized to 1 GHz
1
AV
DD
= DV
DD
= 3 V.
2
Guaranteed by design. Sample tested to ensure compliance.
3
T
A
= 25°C; AV
DD
= DV
DD
= 3 V; RF
IN
= 350 MHz. The current for any other setup (25°C, 3.0 V) in mA is given by 2.35 + 0.0046 (REF
IN
) + 0.0062 (RF); RF frequency and REF
IN
frequency in MHz.
4
All phase noise measurements were performed with a Rohde & Schwarz FSUP26 phase noise test system using the EVAL-ADF4002EBZ1 evaluation board and the
ultralow noise, 100 MHz OCXO from Wenzel (Part No. 501-16843) as the PLL reference.
5
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value)
and 10logf
PFD
. PN
SYNTH
= PN
TOT
− 10logf
PFD
− 20logN.
6
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (f
RF
) and at a
frequency offset (f) is given by PN = P
1_f
+ 10log(10 kHz/f) + 20log(f
RF
/1 GHz). Both the normalized phase noise floor and the flicker noise are modeled in ADIsimPLL.
P1-P3P4-P6P7-P8

ADF4002SRU-EP

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Buy ADF4002SRU-EP
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL Phase Detect / PLL Freq Synthesizer
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