ADF4002-EP
Rev. 0 | Page 6 of 8
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
R
SET
CP
CPGND
AGND
MUXOUT
LE
DATA
CLK
CE
DGND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
RF
IN
B
RF
IN
A
AV
DD
REF
IN
V
P
DV
DD
ADF4002-EP
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
09187-002
Figure 3. Pin Configuration (Top View)
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 R
SET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the R
SET
pin is 0.66 V. The relationship between I
CP
and R
SET
is
SET
MAXCP
R
I
25.5
=
where R
SET
= 5.1 kΩ and I
CP MAX
= 5 mA.
2 CP
Charge Pump Output. When enabled, this output provides ±I
CP
to the external loop filter that, in turn, drives
the external VCO.
3 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 AGND Analog Ground. This is the ground return path of the RF input.
5 RF
IN
B
Complementary Input to the RF Input. This pin must be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF.
6 RF
IN
A Input to the RF Input. This small-signal input is ac-coupled to the external VCO.
7 AV
DD
Analog Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to the AV
DD
pin. AV
DD
must be the same value as DV
DD
.
8 REF
IN
Reference Input. This CMOS input has a nominal threshold of AV
DD
/2 and a dc equivalent input resistance
of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
9 DGND Digital Ground.
10 CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-
state mode. Taking this pin high powers up the device, depending on the status of the Power-Down Bit PD1.
11 CLK
Serial Clock Input. The serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 DATA
Serial Data Input. The serial data is loaded MSB first; the two LSBs are the control bits. This input is a high
impedance CMOS input.
13 LE
Load Enable. When LE goes high, the data stored in the shift registers is loaded into one of the four latches;
the latch is selected using the control bits. This input is a high impedance CMOS input.
14 MUXOUT
Multiplexer Output. This output allows the lock detect, the scaled RF, or the scaled reference frequency to
be accessed externally.
15 DV
DD
Digital Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to the DV
DD
pin. DV
DD
must be the same value as AV
DD
.
16 V
P
Charge Pump Power Supply. This should be greater than or equal to AV
DD
. In systems where AV
DD
is 3 V,
V
P
can be set to 5.5 V and used to drive a VCO with a tuning voltage of up to 5 V.
