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ISL29038IROZ-EVALZ

P1-P3P4-P6P7-P9P10-P12P13-P15
ISL29038
4
FN7851.1
January 23, 2015
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ProxWASH Washout Bit Activation Level Norwood Solar Emulator 40k Lux
ProxOffsetMax Maximum PROX Offset, Referenced to
Proximity ADC Range
512 LSB
ProxOffsetInc Proximity Offset Adjust Increment Referenced
to Proximity ADC Range
27 LSB
LED DRIVER (IRDR PIN)
t
r
Rise Time for IRDR Sink Current R
LOAD
= 15Ω at IRDR pin, 20% to 80% 25 ns
t
f
Fall time for IRDR Sink Current R
LOAD
= 15Ω at IRDR pin, 80% to 20% 15 ns
I
IRDR_0
IRDR Sink Current PROX_DR = 0; V
IRDR
= 0.5V 31.25 mA
I
IRDR_1
IRDR Sink Current PROX_DR = 1; V
IRDR
= 0.5V 62.5 mA
I
IRDR_2
IRDR Sink Current PROX_DR = 2; V
IRDR
= 0.5V 125 mA
I
IRDR_3
IRDR Sink Current PROX_DR = 3; V
IRDR
= 0.5V 250 mA
I
IRDR_LEAK
IRDR Leakage Current PROX_EN = 0; V
IRDR
= 3.63V 0.001 1 µA
V
IRDR
IRDR Pin Voltage Compliance Register bit PROX_DR = 0 0.50 4.3 V
t
PULSE
I
IRDR
On Time Per PROX Reading 90 µs
MISCELLANEOUS
V
REF
Voltage of REXT Pin ALS_EN = 1 or PROX_EN = 1 0.52 V
Electrical Specifications V
DD
= 3.0V, T
A
= +25°C, R
EXT
= 499kΩ 1% tolerance. (Continued)
PARAMETER DESCRIPTION TEST CONDITION
MIN
(Note 7
)TYP
MAX
(Note 7)UNITS
I
2
C Electrical Specifications For SCL and SDA unless otherwise noted, V
DD
= 3V, T
A
= +25°C, R
EXT
= 499kΩ 1% tolerance
(Note 11
).
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
V
I
2
C
Supply Voltage Range for I
2
C Interface 1.7 3.63 V
f
SCL
SCL Clock Frequency 400 kHz
V
IL
SCL and SDA Input Low Voltage 0.55 V
V
IH
SCL and SDA Input High Voltage 1.25 V
V
hys
Hysteresis of Schmitt Trigger Input 0.05V
DD
V
V
OL
Low-level Output Voltage (open-drain) at 4mA Sink
Current
0.4 V
I
i
Input Leakage for each SDA, SCL Pin -10 10 µA
t
SP
Pulse Width of Spikes that must be Suppressed by
the Input Filter
50 ns
t
AA
SCL Falling Edge to SDA Output Data Valid 900 ns
C
i
Capacitance for each SDA and SCL Pin 10 pF
t
HD:STA
Hold Time START Condition After this period, the first clock
pulse is generated
600 ns
t
LOW
LOW Period of the SCL Clock Measured at the 30% of VDD
crossing
1300 ns
t
HIGH
HIGH Period of the SCL Clock 600 ns
t
SU:STA
Set-up Time for a START Condition 600 ns
t
HD:DAT
Data Hold Time 30 ns
t
SU:DAT
Data Set-up Time 100 ns
ISL29038
5
FN7851.1
January 23, 2015
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t
R
Rise Time of both SDA and SCL Signals (Note 12) 20 + 0.1xC
b
ns
t
F
Fall Time of both SDA and SCL Signals (Note 12) 20 + 0.1xC
b
ns
t
SU:STO
Set-up Time for STOP Condition 600 ns
t
BUF
Bus Free Time Between a STOP and START Condition 1300 ns
C
b
Capacitive Load for Each Bus Line 400 pF
R
pull-up
SDA and SCL System Bus Pull-Up Resistor Maximum determined by t
R
and t
F
1kΩ
t
VD;DAT
Data Valid Time 0.9 µs
t
VD:ACK
Data Valid Acknowledge Time 0.9 µs
V
nL
Noise Margin at the LOW Level 0.1VDD V
V
nH
Noise Margin at the HIGH Level 0.2VDD V
NOTES:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
8. Cover glass assumes fixed infrared/visible light transmissivity ratio of 10.
9. The LED light source irradiance is calibrated to produce the same ALS count as a fluorescent light source of the same Lux level.
10. An 850nm infrared LED is used in production test for proximity/IR sensitivity testing.
11. All parameters in I
2
C Electrical Specifications table are guaranteed by design and simulation.
12. C
b
is the capacitance of the bus in pF.
I
2
C Electrical Specifications For SCL and SDA unless otherwise noted, V
DD
= 3V, T
A
= +25°C, R
EXT
= 499kΩ 1% tolerance
(Note 11
). (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
FIGURE 4. I
2
C TIMING DIAGRAM
ISL29038
6
FN7851.1
January 23, 2015
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ISL29038 Configuration and
Control
I
2
C Interface
ISL29038 configuration and control is performed using the I2C
or SMBus. The ISL29038’s I2C interface slave address is
internally hard wired as 8’b1000100x, where x denotes the R/W
bit.
Every I2C transaction begins with the master asserting a start
condition (SDA falling while SCL remains high). The first
transmitted byte is initiated by the master and includes 7
address bits and a R/W bit. The slave is responsible for pulling
SDA low during the ACK time after every transmitted byte.
Figure 5 shows a sample one-byte read. The I2C bus master
always drives the SCL (clock) line, while either the master or the
slave can drive the SDA (data) line.
Each I
2
C transaction ends with the master asserting a stop
condition (SDA rising while SCL remains high). For more
information about the I
2
C standard, consult the Philips
™
I
2
C
specification documents.
Timing specifications are included in “
I
2
C Electrical
Specifications” on page 4. The timing parameters are defined in
Figure 4
.
The I
2
C interface on the ISL29038 supports single and multiple
byte read and write transfers using the random-read/write
protocol. The ISL29038 does not support I
2
C ‘Repeat Start’
protocol.
NOTE: That in most system implementations, the ISL29038 is connected
to a single I
2
C master with one or more slave devices, consequently,
absence of ‘Repeat Start’ function does not adversely affect I
2
C bus
system performance.
FIGURE 5. I
2
C DRIVER TIMING DIAGRAM FOR MASTER AND SLAVE CONNECTED TO COMMON BUS
START
W
A A
A6 A5 A4 A3 A2 A1 A0 W
A R7 R6 R5 R4 R3 R2 R1 R0 A A6 A5 A4 A3 A2 A1 A0 W A
A A AD7D6D5D4D3D2D1D0
1357
1357 123456 9246
STOP START
SDA DRIVEN BY MASTER
DEVICE ADDRESS
SDA DRIVEN BY ISL29038
DATA BYTE0REGISTER ADDRESS
SLAVE
DEVICE ADDRESS
I
2
C DATA
SDA DRIVEN BY MASTER
SDA DRIVEN BY MASTER
2468
924689 78135789
I
2
C SDA
I
2
C SDA
I
2
C CLK
MASTER
(ISL29038)
P1-P3P4-P6P7-P9P10-P12P13-P15

ISL29038IROZ-EVALZ

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Manufacturer:
Renesas / Intersil
Description:
Optical Sensor Development Tools ISL29038IROZ-EVALZ (PB-Free ) EVALUATION BOARD - ROHs Compli
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