74LVC169 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 29 November 2012 14 of 24
NXP Semiconductors
74LVC169
Presettable synchronous 4-bit up/down binary counter
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8
.
Logic levels: V
OL
and V
OH
are the typical output voltage levels that occur with the output load.
Fig 11. Set-up and hold times for the input (Dn) and parallel enable input (PE)
001aaa654
GND
GND
GND
t
h
t
h
t
su
t
su
t
su
t
h
t
h
t
su
V
M
V
M
V
M
V
I
V
I
CP input
PE input
Dn input
V
I
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8
.
Logic levels: V
OL
and V
OH
are the typical output voltage levels that occur with the output load.
Fig 12. Set-up and hold times for count enable inputs (CEP and CET) and control input (U/D)
001aaa655
t
h
t
su
t
h
t
su
GND
V
I
V
M
V
M
GND
V
I
CP input
CEP, CET, U/D input
Table 8. Measurement points
Supply voltage Input Output
V
CC
V
I
V
M
V
M
1.2 V V
CC
0.5 V
CC
0.5 V
CC
1.65 V to 1.95 V V
CC
0.5 V
CC
0.5 V
CC
2.3 V to 2.7 V V
CC
0.5 V
CC
0.5 V
CC
2.7 V 2.7 V 1.5 V 1.5 V
3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V
