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74LVC169DB,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
74LVC169 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 29 November 2012 4 of 24
NXP Semiconductors
74LVC169
Presettable synchronous 4-bit up/down binary counter
Fig 3. Logic diagram
001aaa649
D
CP
Q
Q
D
CP
Q
Q
D
CP
Q
Q
D
CP
Q
Q
Q0
14
Q1
13
Q2
12
Q3
11
TC
15
U/D
1
CP
2
CET
10
CEP
7
PE
9
D3
6
D2
5
D1
4
D0
3
74LVC169 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 29 November 2012 5 of 24
NXP Semiconductors
74LVC169
Presettable synchronous 4-bit up/down binary counter
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4. Pin configuration for SO16 and (T)SSOP16 Fig 5. Pin configuration for DHVQFN16
001aaa682
74LVC169
CEP CET
D3 Q3
D2
GND
(1)
Q2
D1 Q1
D0 Q0
CP TC
GND
PE
U/D
V
CC
Transparent top view
7 10
6 11
5 12
4
13
3 14
2 15
8
9
1
16
terminal 1
index area
Table 2. Pin description
Symbol Pin Description
U/D
1 up/down control input
CP 2 clock input (LOW-to-HIGH, edge-triggered)
D0 to D3 3, 4, 5, 6 data input
CEP
7 count enable input (active LOW)
GND 8 ground (0 V)
PE
9 parallel enable input (active LOW)
CET
10 count enable carry input (active LOW)
Q0 to Q3 14, 13, 12, 11 flip-flop output
TC
15 terminal count output (active LOW)
V
CC
16 supply voltage
74LVC169 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 29 November 2012 6 of 24
NXP Semiconductors
74LVC169
Presettable synchronous 4-bit up/down binary counter
6. Functional description
[1] H = HIGH voltage level steady state
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level steady state
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
qn = Lower case letters indicate state of referenced output prior to the LOW-to-HIGH clock transition
X = don’t care
= LOW-to-HIGH clock transition
* = The TC
is LOW when CET is LOW and the counter is at terminal count
Terminal count up is (HHHH) and terminal count down is (LLLL)
Table 3. Function table
[1]
Operating mode Input Output
CP U/D CEP CET PE Dn Qn TC
Parallel load (Dn to Qn) XXXI I L *
XXXl hH *
Count up (increment) h I I h X count up *
Count down (decrement) I I I h X count down *
Hold (do nothing) XhXhXqn *
XXXhXqn H
Fig 6. State diagram
001aaa647
0
15
14
13
12
1 2 3 4
5
6
7
11
count down
count up
10 9 8
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74LVC169DB,118

Mfr. #:
Buy 74LVC169DB,118
Manufacturer:
NXP Semiconductors
Description:
Counter ICs 3.3V SYNC 4-BIT BIN
Lifecycle:
New from this manufacturer.
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