Current-Mode Control Loop
The advantages of current-mode control over voltage-
mode control are twofold. First, there is the feed-for-
ward characteristic brought on by the controller’s
ability to adjust for variations in the input voltage on a
cycle-by-cycle basis. Secondly, the stability require-
ments of the current-mode controller are reduced to
that of a single-pole system unlike the double pole in
voltage-mode control.
The MAX15000/MAX15001 use a current-mode control
loop where the output of the error amplifier (COMP) is
compared to the current-sense voltage at CS. When the
current-sense signal is lower than the noninverting
input of the PWM comparator, the output of the CPWM
comparator is low and the switch is turned on at each
clock pulse. When the current-sense signal is higher than
the inverting input of the CPWM, the output of the CPWM
comparator goes high and the switch is turned off.
Undervoltage Lockout
The MAX15000/MAX15001 provide a UVLO/EN input.
The threshold for UVLO is 1.23V with 60mV hysteresis.
Before any operation can commence, the voltage on
UVLO/EN has to exceed 1.23V. The UVLO circuit keeps
the CPWM comparator, ILIM comparator, oscillator,
and output driver shut down to reduce current con-
sumption (see the Functional Diagram).
Use this UVLO/EN input to program the input-supply
start voltage. For example, a reasonable start voltage
for a 36V to 72V telecom range is usually 34V.
Calculate the resistor-divider values, R2 and R3 (see
Figure 1) by using the following formulas:
where I
UVLO
is the UVLO/EN input current (50nA max),
and V
ULR2
is the UVLO/EN wake-up threshold (1.23V).
V
IN
is the value of the input-supply voltage where the
power supply must start. The value of R3 is calculated
to minimize the voltage-drop error across R2 as a result
of the input bias current of the UVLO/EN input.
MAX15000 Bootstrap UVLO
In addition to the externally programmable UVLO func-
tion offered in both the MAX15000 and MAX15001, the
MAX15000 includes an internal bootstrap UVLO that is
very useful when designing high-voltage power sup-
plies (see the Functional Diagram). This allows the
device to bootstrap itself during initial power-up. The
MAX15000 attempts to start when V
IN
exceeds the
bootstrap UVLO threshold of 21.6V. During startup, the
UVLO circuit keeps the CPWM comparator, ILIM com-
parator, oscillator, and output driver shut down to
reduce current consumption. Once V
IN
reaches 21.6V,
the UVLO circuit turns on the CPWM and ILIM com-
parators, the oscillator, and allows the output driver to
switch. If V
IN
drops below 1.17V, the UVLO circuit shuts
down the CPWM comparator, ILIM comparator, oscilla-
tor, and output driver returning the MAX15000 to the
low-current startup mode.
Startup Operation
The MAX15001 starts up when the voltage at IN
exceeds 9.5V and the UVLO/EN input is greater than
1.23V. However, the MAX15000 requires that, in addi-
tion to meeting the specified startup conditions for the
MAX15001, the voltage at IN exceeds the bootstrap
UVLO threshold of 21.6V.
For the MAX15000, the voltage at IN is normally derived
from a tertiary winding of the transformer. However, at
startup there is no energy being delivered through the
transformer, hence, a special bootstrap sequence is
required. Figure 2 shows the voltages at IN and V
CC
during startup. Initially, both V
IN
and V
CC
are 0V. After
the line voltage is applied, C1 charges through the
startup resistor, R1, to an intermediate voltage. At this
point, the internal regulator begins charging C2 (see
Figure 1). Only 50µA of the current supplied through R1
is used by the MAX15000, the remaining input current
charges C1 and C2. The charging of C2 stops when
the V
CC
voltage reaches approximately 9.5V, while the
voltage across C1 continues rising until it reaches the
wake-up level of 21.6V. Once V
IN
exceeds the boot-
strap UVLO threshold, NDRV begins switching the
MOSFET and transfers energy to the secondary and
tertiary outputs. If the voltage on the tertiary output
builds to higher than 9.74V (the bootstrap UVLO lower
