Addressing
GDDR6 addressing is defined for a single channel with devices having two channels per
device.
Table 3: Addressing
Parameter
8Gb Density
x16 Mode x8 Mode
Number of channels 2
Memory density (per channel) 4Gb
Memory prefetch (per channel) 256b 128b
Bank address (per channel) BA[3:0]
Row address (per channel) R[13:0]
Column address (per channel) C[5:0] C[6:0]
Page size (per channel) 2KB
Refresh 16k/32ms
Notes:
1. The column address notation for GDDR6 does not include the lower four address bits as
the burst order is always fixed for READ and WRITE.
2. Page size = 2^COLBITS × (Prefetch_Size/8) where COLBITS is the number of column ad-
dress bits.
8Gb: 2 Channels x16/x8 GDDR6 SGRAM
Functional Description
CCMTD-1412786195-10191
gddr6_sgram_8gb_brief.pdf - Rev. F 8/18 EN
8
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