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MT61K256M32JE-13:A

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Figure 4: Clocking and Interface Relationship
CK_c
CK_t
DQ, DBI_n
EDC
CA
QDR WCK
DDR WCK
f (for example, 1.5 GHz)
2f (for example, 3 Gb/s)
2f (for example, 3 GHz)
4f (for example, 6 GHz)
8f (for example, 12 Gb/s)
4f (for example, 6 Gb/s)
Note:
1. The figure shows the relationship between the data rate of the buses and the clocks; it
is not a timing diagram.
Figure 5: Block Diagram of an Example Clock System
GDDR6 SGRAM
CA
(3 Gb/s)
to internal
state machine
CMD/ADD
ADD/CMD sampled by CK_t/CK_c as DDR
CK_t, CK_c
(1.5 GHz)
6 GHz)
D Q
WCK_t, WCK_c
(3 GHz or
to EDC pin
WCK2CK
Alignment
/2
/4
PLL
Internal WCK
3.0 GHz
PLL
Data Tx/Rx
DRAM
Core
Controller
DQ
D Q
clock
phase
ctrl
WRITE
data
clock
phase
ctrl
READ
data
DATA
(12 Gb/s)
ADD/CMD centered with CK_t/CK_c
D Q
D Q
Osc.
DQ
early/
late
D Q
8Gb: 2 Channels x16/x8 GDDR6 SGRAM
Functional Description
CCMTD-1412786195-10191
gddr6_sgram_8gb_brief.pdf - Rev. F 8/18 EN
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
Addressing
GDDR6 addressing is defined for a single channel with devices having two channels per
device.
Table 3: Addressing
Parameter
8Gb Density
x16 Mode x8 Mode
Number of channels 2
Memory density (per channel) 4Gb
Memory prefetch (per channel) 256b 128b
Bank address (per channel) BA[3:0]
Row address (per channel) R[13:0]
Column address (per channel) C[5:0] C[6:0]
Page size (per channel) 2KB
Refresh 16k/32ms
Notes:
1. The column address notation for GDDR6 does not include the lower four address bits as
the burst order is always fixed for READ and WRITE.
2. Page size = 2^COLBITS × (Prefetch_Size/8) where COLBITS is the number of column ad-
dress bits.
8Gb: 2 Channels x16/x8 GDDR6 SGRAM
Functional Description
CCMTD-1412786195-10191
gddr6_sgram_8gb_brief.pdf - Rev. F 8/18 EN
8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
Operations
Command Truth Table
GDDR6 uses a packetized DDR command/address bus that encodes all commands and
addresses on a 10-bit CA bus as outlined in the table below.
Figure 6: Command Truth Table
NO OPERATION
MODE REGISTER SET
Operation
ACTIVATE
READ
READ with
AUTO PRECHARGE
LOAD FIFO
READ TRAINING
WRITE
WRITE with
AUTO PRECHARGE
WRITE SINGLE
BYTE MASK
NOP (1)
NOP (2)
NOP (3)
MRS
Symbol
ACT
RD
RDA
LDFF
RDTR
WOM
WOMA
R
F
R
F
R
F
R
F
R
F
R
F
R
F
R
F
R
F
R
F
R
F
R
F
R
F
R
F
CK
Edge
L
L
L
L
n - 1
L
L
L
L
L
L
L
L
L
L
L
L
n
CKE_n
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
R13
L
L
L
H
L
H
L
H
L
H
L
H
CA9
H
H
H
H
L
H
H
H
H
H
H
L
L
H
L
V
R12
H
H
H
H
H
H
H
H
H
L
H
L
H
L
H
CA8
H
H
H
L
V
V
V
V
V
V
OP11
BA3
BA3
BA3
BA3
BA3
R11
L
L
B3
H
V
H
L
L
L
Byte 0
BST7
CA7
BA3
Byte 0
BST15
Byte 1
BST7
Byte 1
BST15
M3
V
V
V
V
V
V
OP10
BA2
BA2
BA2
BA2
BA2
R10
L
L
B2
L
V
H
L
L
H
CA6
BA2
Byte 0
BST6
Byte 0
BST14
Byte 1
BST6
Byte 1
BST14
M2
V
V
V
V
V
V
OP9
BA1
BA1
BA1
BA1
BA1
R9
V
V
B1
D9
V
V
V
V
V
BA1
Byte 0
BST5
Byte 0
BST13
Byte 1
BST5
Byte 1
BST13
M1
V
V
V
V
V
V
OP8
BA0
BA0
BA0
BA0
BA0
R8
L
H
B0
D8
V
L
L
H
L
BA0
Byte 0
BST4
Byte 0
BST12
Byte 1
BST4
Byte 1
BST12
M0
V
V
V
V
V
V
OP7
R3
R7
C3
CE
C3
CE
D3
D7
V
CE
C3
CE
C3
CE
C3
CE
Byte 0
BST3
Byte 0
BST11
Byte 1
BST3
Byte 1
BST11
OP3
V
V
V
V
V
V
OP6
R2
R6
C2
C6
C2
C6
D2
D6
V
V
C2
C6
C2
C6
C2
C6
Byte 0
BST2
Byte 0
BST10
Byte 1
BST2
Byte 1
BST10
OP2
V
V
V
V
V
V
OP5
R1
R5
C1
C5
C1
C5
D1
D5
V
V
C1
C5
C1
C5
C1
C5
Byte 0
BST1
Byte 0
BST9
Byte 1
BST1
Byte 1
BST9
OP1
V
V
V
V
V
V
OP4
R0
R4
C0
C4
C0
C4
D0
D4
V
V
C0
C4
C0
C4
C0
C4
Byte 0
BST0
Byte 0
BST8
Byte 1
BST0
Byte 1
BST8
OP0
1, 10
1, 2, 3
1, 2, 4
1, 2, 5,
6
1, 2, 5,
6
1, 2, 8
1, 2, 6
1, 2, 5,
6
1, 2, 5,
6
1, 2, 5,
6
CA5
CA4
CA3
CA2
CA1
CA0
Notes
WSM
8Gb: 2 Channels x16/x8 GDDR6 SGRAM
Functional Description
CCMTD-1412786195-10191
gddr6_sgram_8gb_brief.pdf - Rev. F 8/18 EN
9
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2016 Micron Technology, Inc. All rights reserved.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

MT61K256M32JE-13:A

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Micron
Description:
IC RAM 8G PARALLEL 1.625GHZ
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