LTC4061
16
4061fd
It is important to remember that LTC4061 applications do
not need to be designed for worst-case thermal conditions,
since the IC will automatically reduce power dissipation if
the junction temperature reaches approximately 105°C.
Thermistors
The LTC4061 NTC comparator trip points were designed
to work with thermistors whose resistance-temperature
characteristics follow Vishay Dale’s “R-T Curve 1.” The
Vishay NTHS0603N01N1003J is an example of such a
thermistor. However, Vishay Dale has many thermistor
products that follow the “R-T Curve 1” characteristic in a
variety of sizes. Furthermore, any thermistor whose ratio
of R
COLD
to R
HOT
is about 6 also works (Vishay Dale R-T
Curve 1 shows a ratio of R
COLD
to R
HOT
of 3.266/0.5325
= 6.13).
Power conscious designers may want to use thermistors
whose room temperature value is greater than 10kΩ.
Vishay Dale has a number of values of thermistor from
10kΩ to 100kΩ that follow the “R-T Curve 1.” Using dif-
ferent R-T curves, such as Vishay Dale “R-T Curve 2,” is
also possible. This curve, combined with LTC4061 internal
thresholds, gives temperature trip points of approximately
0°C (falling) and 40°C (rising), a delta of 40°C. This delta in
temperature can be moved in either direction by changing
the value of R
NOM
with respect to R
NTC
. Increasing R
NOM
moves both trip points to lower temperatures. Likewise
a decrease in R
NOM
with respect to R
NTC
moves the trip
points to higher temperatures. To calculate R
NOM
for a shift
to lower temperatures, use the following equation:
R
R
R at C
NOM
COLD
NTC
= °
3 266
25
.
where R
COLD
is the resistance ratio of R
NTC
at the desired
cold temperature trip point. If you want to shift the trip points
to higher temperatures, use the following equations:
R
R
R at C
NOM
HOT
NTC
= °
0 5325
25
.
where R
HOT
is the resistance ratio of R
NTC
at the desired
hot temperature trip point.
Here is an example using 10kΩ R-T Curve 2 thermistor
from Vishay Dale. The difference between the trip points
applicaTions inForMaTion
is 40°C, from before, and we want the cold trip point to
be 0°C, which would put the hot trip point at 40°C. The
R
NOM
needed is calculated as follows:
R
R
R at C
k
NOM
COLD
NTC
= °
= =
3 266
25
2 816
3 266
10 8 62
.
.
.
.Ω kkΩ
The nearest 1% value for R
NOM
is 8.66kΩ. This is the
value used to bias the NTC thermistor to get cold and hot
trip points of approximately 0°C and 40°C respectively.
To extend the delta between the cold and hot trip points, a
resistor, R1, can be added in series with R
NTC
. The values
of the resistors are calculated as follows:
R
R R
R
NOM
COLD HOT
=
=
. .
.
. - .
3 266 0 5325
0 5325
3 266 0 532
1
55
( )R R R
COLD HOT HOT
where R
NOM
is the value of the bias resistor, R
HOT
and
R
COLD
are the values of R
NTC
at the desired temperature
trip points. Continuing the example from before with a
desired hot trip point of 50°C:
R
R R
k
NOM
COLD HOT
= =
. .
( . . )
3 266 0 5325
10 2 816 0 4086
3.. .
. , . % .
266 0 5325
8 8 8 87 1= k k is the nearest valueΩ
R k
1
10
0 5325
3 266 0 5325
2 816 0 4086
=
.
. .
( . . ) 00 4086
604 604 1
.
, % .= Ω is the nearest value
The final solution is R
NOM
= 8.87kΩ, R1 = 604Ω and
R
NTC
= 10kΩ at 25°C.
NTC Trip Point Error
When a 1% resistor is used for R
HOT
, the major error
in the 40°C trip point is determined by the tolerance of
the NTC thermistor. A typical 100kΩ NTC thermistor has
±10% tolerance. By looking up the temperature coef-
ficient of the thermistor at 40°C, the tolerance error can
LTC4061
17
4061fd
applicaTions inForMaTion
be calculated in degrees centigrade. Consider the Vishay
NTHS0603N01N1003J thermistor, which has a temperature
coefficient of 4%/°C at 40°C. Dividing the tolerance by
the temperature coefficient, ±5%/(4%/°C) = ±1.25°C, gives
the temperature error of the hot trip point.
The cold trip point error depends on the tolerance of the
NTC thermistor and the degree to which the ratio of its
value at 0°C and its value at 40°C varies from 6.14 to 1.
Therefore, the cold trip point error can be calculated us-
ing the tolerance, TOL, the temperature coefficient of the
thermistor at 0°C, TC (in %/°C), the value of the thermistor
at 0°C, R
COLD
, and the value of the thermistor at 40°C,
R
HOT
. The formula is:
Temperature Error C
TOL
R
R
COLD
HOT
( )
.
° =
+
1
6 14
1
100
TC
For example, the Vishay NTHS0603N01N1003J thermistor
with a tolerance of ±5%, TC of -5%/°C and R
COLD
/ R
HOT
of 6.13, has a cold trip point error of:
Temperature Error C( )
.
.
.
° =
+
1 0 05
6 14
6 13 1 10
00
5
0 95 1 05
. , .= ° °C C
Thermal Considerations
In order to deliver maximum charge current under all
conditions, it is critical that the exposed metal pad on the
backside of the LTC4061 package is properly soldered to
the PC board ground. Correctly soldered to a 2500mm
2
double sided 1oz copper board, the LTC4061 has a ther-
mal resistance of approximately 40°C/W. Failure to make
thermal contact between the exposed pad on the backside
of the package and the copper board will result in thermal
resistances far greater than 40°C/W. As an example, a
correctly soldered LTC4061 can deliver over 800mA to a
battery from a 5V supply at room temperature. Without
a good backside thermal connection, this number could
drop to less than 500mA.
V
CC
Bypass Capacitor
Many types of capacitors can be used for input bypassing;
however, caution must be exercised when using multilayer
ceramic capacitors. Because of the self-resonant and high
Q characteristics of some types of ceramic capacitors, high
voltage transients can be generated under some start-up
conditions such as connecting the charger input to a live
power source. Adding a 1.5Ω resistor in series with an X5R
ceramic capacitor will minimize start-up voltage transients.
For more information, see Application Note 88.
Charge
Current Soft-Start and Soft-Stop
The LTC4061 includes a soft-start circuit to minimize the
inrush current at the start of a charge cycle. When a charge
cycle is initiated, the charge current ramps from zero to the
full-scale current over a period of approximately 100µs.
Likewise, internal circuitry slowly ramps the charge cur-
rent from full-scale to zero when the charger is shut off
or self terminates. This has the effect of minimizing the
transient current load on the power supply during start-up
and charge termination.
Reverse
Polarity Input Voltage Protection
In some applications, protection from reverse polarity
voltage on V
CC
is desired. If the supply voltage is high
enough, a series blocking diode can be used. In other
cases, where the diode voltage drop must be kept low, a
P-channel MOSFET can be used (as shown in Figure 7).
USB
and Wall Adapter Power
The LTC4061 allows charging from both a wall adapter
and a USB port. Figure 8 shows an example of how to
combine wall adapter and USB power inputs. A P-channel
V
CC
V
IN
4061 F07
LTC4061
DRAIN-BULK
DIODE OF FET
Figure 7. Low Loss Input Reverse Polarity Protection
LTC4061
18
4061fd
package DescripTion
MOSFET, MP1, is used to prevent back conducting into the
USB port when a wall adapter is present and a Schottky
diode, D1, is used to prevent USB power loss through the
1kΩ pull-down resistor.
Typically a wall adapter can supply more current than
the 500mA limited USB port. Therefore, an N-channel
MOSFET, MN1, and an extra 3.3kΩ program resistor are
used to increase the charge current to 800mA when the
wall adapter is present.
+
V
CC
D1
PROG
I
DET
3.3k
2k
MN1
5V WALL
ADAPTER
I
CHG
= 800mA
USB POWER
I
CHG
= 500mA
MP1
4061 F08
BAT
LTC4061
1.25k
Li-Ion
BATTERY
SYSTEM
LOAD
1k
C/5
Figure 8. Combining Wall Adapter and USB Power
3.00 p0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 p 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 p 0.10
(2 SIDES)
0.75 p0.05
R = 0.125
TYP
2.38 p0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD) DFN REV C 0310
0.25 p 0.05
2.38 p0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 p0.05
(2 SIDES)2.15 p0.05
0.50
BSC
0.70 p0.05
3.55 p0.05
PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
PIN 1 NOTCH
R = 0.20 OR
0.35 s 45o
CHAMFER
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)

LTC4061EDD#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management St&alone Lin Li-Ion Bat Chr w/ Thermisto
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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