XC4000, XC4000A, XC4000H Logic Cell Array Families
2-28
The XC4000 family introduces an additional option: When
this option is enabled, the user can externally hold the
open-drain DONE output Low, and thus stall all further
progress in the Start-up sequence, until DONE is released
and has gone High. This option can be used to force
synchronization of several LCA devices to a common user
clock, or to guarantee that all devices are successfully
configured before any I/Os go active.
Start-up Sequence
The Start-up sequence begins when the configuration
memory is full, and the total number of configuration clocks
received since INIT went High equals the loaded value of
the length count. The next rising clock edge sets a flip-flop
Q0 (see Figure 22), the leading bit of a 5-bit shift register.
The outputs of this register can be programmed to control
three events.
• The release of the open-drain DONE output,
• The change of configuration-related pins to the
user function, activating all IOBs.
• The termination of the global Set/Reset initialization
of all CLB and IOB storage elements.
The DONE pin can also be wire-ANDed with DONE pins of
other LCA devices or with other external signals, and can
then be used as input to bit Q3 of the start-up register. This
is called “Start-up Timing Synchronous to Done In” and
labeled: CCLK_SYNC or UCLK_SYNC. When DONE is
not used as an input, the operation is called Start-up
Timing Not Synchronous to DONE In, and is labeled
CCLK_NOSYNC or UCLK_NOSYNC. These labels are
not intuitively obvious.
As a configuration option, the start-up control register
beyond Q0 can be clocked either by subsequent CCLK
pulses or from an on-chip user net called STARTUP.CLK.
Start-up from CCLK
If CCLK is used to drive the start-up, Q0 through Q3
provide the timing. Heavy lines in Figure 21 show the
default timing which is compatible with XC2000 and XC3000
devices using early DONE and late Reset.The thin lines
indicate all other possible timing options.
Start-up from a User Clock (STARTUP.CLK)
When, instead of CCLK, a user-supplied start-up clock is
selected, Q1 is used to bridge the unknown phase relation-
ship between CCLK and the user clock. This arbitration
causes an unavoidable one-cycle uncertainty in the timing
of the rest of the start-up sequence.
tion data bits and a 4-bit frame error field. If a frame data
error is detected, the LCA device halts loading, and signals
the error by pulling the open-drain
INIT pin Low.
After all configuration frames have been loaded into an
LCA device, DOUT again follows the input data so that the
remaining data is passed on to the next device.
Start-Up
Start-up is the transition from the configuration process to
the intended user operation. This means a change from
one clock source to another, and a change from interfacing
parallel or serial configuration data where most outputs are
3-stated, to normal operation with I/O pins active in the
user-system. Start-up must make sure that the user-logic
“wakes up” gracefully, that the outputs become active
without causing contention with the configuration signals,
and that the internal flip-flops are released from the global
Reset or Set at the right time.
Figure 21 describes Start-up timing for the three Xilinx
families in detail.
The XC2000 family goes through a fixed sequence:
DONE goes High and the internal global Reset is de-
activated one CCLK period after the I/O become active.
The XC3000A family offers some flexibility: DONE can be
programmed to go High one CCLK period before or after
the I/O become active. Independent of DONE, the internal
global Reset is de-activated one CCLK period before or
after the I/O become active.
The XC4000 family offers additional flexibility: The three
events, DONE going High, the internal Reset/Set being
de-activated, and the user I/O going active, can all occur
in any arbitrary sequence, each of them one CCLK period
before or after, or simultaneous with, any of the other.
The default option, and the most practical one, is for DONE
to go High first, disconnecting the configuration data
source and avoiding any contention when the I/Os become
active one clock later. Reset/Set is then released another
clock period later to make sure that user-operation starts
from stable internal conditions. This is the most common
sequence, shown with heavy lines in Figure 21, but the
designer can modify it to meet particular requirements.
The XC4000 family offers another start-up clocking option:
The three events described above don’t have to be trig-
gered by CCLK, they can, as a configuration option, be
triggered by a user clock. This means that the device can
wake up in synchronism with the user system.
