XC4000, XC4000A, XC4000H Logic Cell Array Families
2-34
XC4000
+5 V
M0 M1
CCLK
DIN
STRB
D0
D1
D2
D3
D4
D5
D6
D7
RESET
I/O
PORT
MICRO
COMPUTER
DOUT
HDC
LDC
M2
•
•
•
OTHER
I/O PINS
PROGRAM
TO CCLK OF OPTIONAL
DAISY-CHAINED LCA DEVICES WITH
DIFFERENT CONFIGURATIONS
DONE
+5 V
INIT
TO DIN OF OPTIONAL
SLAVE LCA DEVICES WITH
IDENTICAL CONFIGURATION
X3393
TO CCLK OF OPTIONAL
SLAVE LCA DEVICES WITH
IDENTICAL CONFIGURATION
TO DIN OF OPTIONAL
DAISY-CHAINED LCA DEVICES
WITH DIFFERENT CONFIGURATIONS
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input(s) of the LCA device(s). The serial configuration
bitstream must be available at the DIN input of the lead
LCA device a short set-up time before each rising CCLK
edge. The lead LCA device then presents the preamble
data (and all data that overflows the lead device) on its
DOUT pin.
There is an internal delay of 0.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next LCA device in the daisy-chain accepts data on the
subsequent rising CCLK edge.
How to Delay Configuration After Power-Up
There are two methods to delay configuration after power-
up: Put a logic Low on the
PROGRAM input, or pull the
bidirectional
INIT pin Low, using an open-collector (open-
drain) driver. (See also Figure 20 on page 2-27.)
A Low on the
PROGRAM input is the more radical ap-
proach, and is recommended when the power-supply rise
time is excessive or poorly defined. As long as
PROGRAM
is Low, the XC4000 device keeps clearing its configuration
memory. When
PROGRAM goes High, the configuration
memory is cleared one more time, followed by the begin-
ning of configuration, provided the INIT input is not exter-
nally held Low. Note that a Low on the
PROGRAM input
automatically forces a Low on the
INIT output.
Using an open-collector or open-drain driver to hold
INIT
Low before the beginning of configuration, causes the LCA
device to wait after having completed the configuration
memory clear operation. When
INIT is no longer held Low
externally, the device determines its configuration mode
by capturing its status inputs, and is ready to start the
configuration process. A master device waits an additional
max 250 µs to make sure that all slaves in the potential
daisy-chain have seen
INIT being High.
