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AD9845BJSTZRL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
REV. B
AD9845B
–9–
CCD MODE AND AUX MODE TIMING
N N+1 N+2 N+9 N+10
t
ID
t
ID
t
S1
t
S2
t
CP
t
INH
t
OD
t
H
N–10 N–9 N–8 N–1 N
NOTES
1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
SHP
SHD
DATACLK
OUTPUT
DATA
CCD
SIGNAL
Figure 5. CCD Mode Timing
CCD
SIGNAL
EFFECTIVE PIXELS
CLPOB
CLPDM
OPTICAL BLACK PIXELS
HORIZONTAL
BLANKING
DUMMY PIXELS EFFECTIVE PIXELS
PBLK
NOTES
1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.
OUTPUT
DATA
EFFECTIVE PIXEL DATA
OB PIXEL DATA DUMMY BLACK EFFECTIVE DATA
Figure 6. Typical CCD Mode Line Clamp Timing
DATACLK
OUTPUT
DATA
VIDEO
SIGNAL
N
N+1
N+2
N+8
N+9
N–10 N–9 N–8 N–1 N
t
ID
t
CP
t
OD
t
H
Figure 7. AUX Mode Timing
REV. B–10–
AD9845B
PIXEL GAIN AMPLIFIER (PxGA) TIMING
FRAME N
LINE 0 LINE 1 LINE 2 LINE M
0101... 2323... 0101...
LINE M–1 LINE 0 LINE 1 LINE 2 LINE M
0101... 2323...
0101...
LINE M–1
0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
FRAME N+1
VD
HD
Figure 8. PxGA Mode 1 (Mosaic Separate) Frame/Line Gain Register Sequence
SHP
HD
3ns MIN
3ns MIN
PxGA GAIN
GAIN0 GAIN1 GAIN0
GAIN3
GAIN2
GAINXGAINX
VD
NOTES
1. MINIMUM PULSEWIDTH FOR HD AND VD IS FIVE PIXEL CYCLES.
2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SETUP TIME IS 3 ns.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.
5 PIXEL MIN
Figure 9. PxGA Mode 1 (Mosaic Separate) Detailed Timing
0101... 2323... 0101...
0101... 2323...
0101...
HD
LINE 0 LINE 1 LINE 2 LINE MLINE M–1 LINE 0 LINE 1 LINE 2 LINE MLINE M–1
EVEN FIELD ODD FIELD
0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
VD
Figure 10. PxGA Mode 2 (Interlace) Frame/Line Gain Register Sequence
SHP
HD
PxGA
GAIN
GAIN0 GAIN1 GAIN0
GAIN3GAIN2
GAINX
GAINX
3ns MIN
3ns MIN
5 PIXEL MIN
VD
NOTES
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING OR FALLING EDGE WILL RESET TO 0101.
3. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.
Figure 11. PxGA Mode 2 (Interlace) Detailed Timing
REV. B
AD9845B
–11–
HD
0 = GAIN0, 1 = GAIN1, 2 = GAIN2
012012012... 012012012......01201
VD
LINE N LINE N+1
Figure 12. PxGA Mode 3 (3-Color) Frame/Line Gain Register Sequence
SHP
HD
5 PIXEL MIN
PxGA
GAIN
GAIN1
VD
GAIN2 GAIN0
GAIN1GAIN0
GAINXGAIN0
GAINX
3ns MIN
5 PIXEL MIN
NOTES
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 012012.
Figure 13. PxGA Mode 3 (3-Color) Detailed Timing
VD
HD
0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
LINE N LINE N+1
012301230123......0123001230123012...
Figure 14. PxGA Mode 4 (4-Color) Frame/Line Gain Register Sequence
SHP
HD
5 PIXEL MIN
PxGA GAIN
GAIN1
VD
GAIN2 GAIN0
GAIN1GAIN0
GAINXGAIN0
GAINX
3ns MIN
5 PIXEL MIN
NOTES
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 01230123.
Figure 15. PxGA Mode 4 (4-Color) Detailed Timing
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD9845BJSTZRL

Mfr. #:
Buy AD9845BJSTZRL
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-Bit 30 MSPS CCD Signal Processor
Lifecycle:
New from this manufacturer.
Delivery:
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