AD9845BJSTZRL Datasheet AD9845BJSTZ, AD9845BJSTZRL | P19-P21

REV. B–18–

AD9845B

Gb Gb

CCD: PROGRESSIVE BAYER

LINE0 GAIN0, GAIN1, GAIN0, GAIN1...

Gb GbBB

LINE1

LINE2

GAIN2, GAIN3, GAIN2, GAIN3...

GAIN0, GAIN1, GAIN0, GAIN1...

MOSAIC SEPARATE COLOR

STEERING MODE

Figure 26. CCD Color Filter Example: Progressive Scan

LINE0 GAIN0, GAIN1, GAIN0, GAIN1...

LINE1

LINE2

GAIN0, GAIN1, GAIN0, GAIN1...

Gb GbBB

LINE0 GAIN2, GAIN3, GAIN2, GAIN3...

LINE1

LINE2

GAIN2, GAIN3, GAIN2, GAIN3...

CCD: INTERLACED BAYER

EVEN FIELD

VD SELECTED COLOR

STEERING MODE

ODD FIELD

Gb GbBB

Figure 27. CCD Color Filter Example: Interlaced

The same Bayer pattern can also be interlaced, and the VD

selected mode should be used with this type of CCD (see

Figure 27). The color steering performs the proper multiplexing

of the R, G, and B gain values (loaded into the PxGA

gain regis-

ters) and is synchronized by the user with vertical (VD) and

horizontal (HD) sync pulses. For more detailed information, see

the PxGA

Timing section. The PxGA

gain for each of the four

channels is variable from –2.5 dB to +9.5 dB, controlled in 64

steps through the serial interface. The PxGA

gain curve is

shown in Figure 28.

PxGA GAIN REGISTER CODE

PxGA GAIN – dB

40 48 58 0 8 16 24 31

–2

–4

(011111)(100000)

Figure 28. PxGA Gain Curve

Variable Gain Amplifier

The VGA stage provides a gain range of 2 dB to 36 dB, program-

mable with 10-bit resolution through the serial digital interface.

Combined with approximately 4 dB from the PxGA

stage, the

total gain range for the AD9845B is 6 dB to 40 dB. The mini-

mum gain of 6 dB is needed to match a 1 V input signal with

the ADC full-scale range of 2 V. When compared to 1 V full-

scale systems (such as ADI’s AD9803), the equivalent gain

range is 0 dB to 34 dB.

The VGA gain curve follows a “linear-in-dB” shape. The exact

VGA gain can be calculated for any gain register value by using

the following equation:

Code Range Gain Equation (dB)

0–1023 Gain = (0.0353)(Code)

As shown in the CCD Mode Specifications, only the VGA gain

range from 2 dB to 36 dB has tested and guaranteed accuracy.

This corresponds to a VGA gain code range of 77 to 1023. The

Gain Accuracy Specifications also include a PxGA

gain of approxi-

mately 3.3 dB, for a total gain range of 6 dB to 40 dB.

VGA GAIN REGISTER CODE

VGA GAIN – dB

127 255 383 511 639 767 895 1023

Figure 29. VGA Gain Curve (Gain from PxGA Not Included)

Optical Black Clamp

The optical black clamp loop is used to remove residual offsets

in the signal chain and to track low frequency variations in the

CCD’s black level. During the optical black (shielded) pixel

interval on each line, the ADC output is compared with a fixed

black level reference selected by the user in the clamp level

256 steps. The resulting error signal is filtered to reduce noise,

and the correction value is applied to the ADC input through a

D/A converter. Normally, the optical black clamp loop is turned

on once per horizontal line, but this loop can be updated more

slowly to suit a particular application. If external digital clamping

is used during the postprocessing, the AD9845B optical black

clamping may be disabled using Bit D5 in the Operation Register

(see the Serial Interface Timing and Internal Register Descrip-

tion section). When the loop is disabled, the clamp level register

may still be used to provide programmable offset adjustment.

Horizontal timing is shown in Figure 6. The CLPOB pulse

should be placed during the CCD’s optical black pixels. It is

recommended that the CLPOB pulse duration be at least

20 pixels wide to minimize clamp noise. Shorter pulsewidths may

REV. B

AD9845B

–19–

AUX1IN

0.1F

VGA GAIN

ADC

VGA

5k

0.4V

INPUT SIGNAL

??V

0.8V

0.4V

MIDSCALE

0dB TO 36dB

Figure 30. AUX1 Circuit Configuration

0dB TO 18dB

AUX2IN

BUFFER

0.1F

VIDEO

SIGNAL

CLAMP LEVEL

LPF

VGA GAIN

ADC

VGA

VIDEO CLAMP

CIRCUIT

CLAMP LEVEL

Figure 31. AUX2 Circuit Configuration

Table VII. VGA Gain Register Used for AUX2 Mode

MSB LSB

D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Gain (dB)

X0 XXXXXXXXX0.0

10000000000.0

∑∑

111111111118.0

be used, but clamp noise may increase and the ability to track

low frequency variations in the black level will be reduced.

A/D Converter

The AD9845B uses high performance ADC architecture, opti-

mized for high speed and low power. Differential nonlinearity

(DNL) performance is typically better than 0.5 LSB, as shown in

TPC 2. Instead of the 1 V full-scale range used by the earlier

AD9801 and AD9803 products from Analog Devices, the

AD9845B’s ADC uses a 2 V input range. Better noise perfor-

mance results from using a larger ADC full-scale range

(see TPC 3).

AUX1 Mode

For applications that do not require CDS, the AD9845B can be

configured to sample ac-coupled waveforms. Figure 30 shows

the circuit configuration for using the AUX1 channel input

(Pin 36). A single 0.1 mF ac-coupling capacitor is needed between

the input signal driver and the AUX1IN pin. An on-chip dc bias

circuit sets the average value of the input signal to approximately

0.4 V, which is referenced to the midscale code of the ADC.

The VGA gain register provides a gain range

of 0 dB to 36 dB in

this mode of operation (see Figure 29). The VGA gains up the

signal level with respect to the 0.4 V bias level. Signal levels

above the bias level will be further increased to a higher ADC

code, while signal levels below the bias level will be further

decreased to a lower ADC code.

AUX2 Mode

For sampling video-type waveforms, such as NTSC and PAL

signals, the AUX2 channel provides black level clamping, gain

adjustment, and A/D conversion. Figure 31 shows the circuit

configuration for using the AUX2 channel input (Pin 34). An

external 0.1 mF blocking capacitor is used with the on-chip video

clamp circuit to level shift the input signal to a desired refer-

ence level. The clamp circuit automatically senses the most

negative portion of the input signal and adjusts the voltage

across the input capacitor. This forces the black level of the

input signal to be equal to the value programmed into the clamp

level register (see the Serial Interface Timing and Internal Register

Description section). The VGA provides gain adjustment from

0 dB to 18 dB. The same VGA gain register is used, but only

the 9 MSBs of the gain register are used (see Table VII.)

REV. B–20–

AD9845B

CCD

CCDIN

BUFFER

OUT

AD9845B

ADC

OUT

DATA

SERIAL

INTERFACE

DIGITAL

OUTPUTS

DIGITAL IMAGE

PROCESSING

ASIC

TIMING

GENERATOR

V-DRIVE

CCD

TIMING

CDS/CLAMP

TIMING

0.1  F

Figure 32. System Applications Diagram

APPLICATIONS INFORMATION

The AD9845B is a complete analog front end (AFE) product

for digital still camera and camcorder applications. As shown in

Figure 32, the CCD image (pixel) data is buffered and sent to

the AD9845B analog input through a series input capacitor.

The AD9845B performs the dc restoration, CDS, gain adjust-

ment, black level correction, and analog-to-digital conversion.

The AD9845B’s digital output data is then processed by the

image processing ASIC. The internal registers of the

AD9845B—used to control gain, offset level, and other

functions—are programmed by the ASIC or microprocessor

through a 3-wire serial digital interface. A system timing

generator provides the clock signals for both the CCD and

the AFE.

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AD9845BJSTZRL

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Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 12-Bit 30 MSPS CCD Signal Processor

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AD9845BJSTZRL

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