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74LVCH32374AEC,551

P1-P3P4-P6P7-P9P10-P12P13-P15
1. General description
The 74LVCH32374A is a 32-bit edge-triggered flip-flop featuring separate D-type inputs
for each flip-flop and 3-state outputs for bus oriented applications. The device consists of
4 sections of 8 edge-triggered flip-flops. A clock (pin nCP) input and an output enable
input (pin nOE
) are provided per 8-bit section. The flip-flops will store the state of their
individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH
nCP transition. When pin nOE
is LOW, the contents of the flip-flops are available at the
outputs. When pin nOE
is HIGH, the outputs go to the high-impedance OFF-state.
Operation of pin nOE
does not affect the state of the flip-flops. The inputs can be driven
from either 3.3 V or 5 V devices. In 3-state operation, the outputs can handle 5 V. These
features allow the use of these devices in a mixed 3.3 V or 5 V environment.
Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused
inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pin-out architecture
Multiple low inductance supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold
High impedance when V
CC
= 0 V
Latch-up performance exceeds 500 mA per JESD 78 Class II
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 Cto+85C and 40 Cto+125C
Packaged in plastic fine-pitch ball grid array package
74LVCH32374A
32-bit edge-triggered D-type flip-flop with 5 V tolerant
inputs/outputs; 3-state
Rev. 3 — 18 December 2012 Product data sheet
74LVCH32374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 18 December 2012 2 of 15
NXP Semiconductors
74LVCH32374A
32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVCH32374AEC 40 C to +125 C LFBGA96 plastic low profile fine-pitch ball grid array package;
96 balls; body 13.5 5.5 1.05 mm
SOT536-1
Fig 1. Logic symbol
coa012
1Q0
FF 1
to 7 other channels
DQ
1OE
1D0
1CP
2Q0
FF 9
to 7 other channels
DQ
2OE
2D0
2CP
3Q0
FF 17
to 7 other channels
DQ
3OE
3D0
3CP
4Q0
FF 25
to 7 other channels
D
CP CP
CP CP
Q
4OE
4D0
4CP
Fig 2. Bus hold circuit
mna473
V
CC
data
input
to internal circuit
74LVCH32374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 18 December 2012 3 of 15
NXP Semiconductors
74LVCH32374A
32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 3. Pin configuration
001aah180
1D1 1D3 1D5 1D7 2D1 2D3 2D5 2D6 3D1 3D3 3D5 3D7 4D1 4D3 4D5 4D6
1D0 1D2 1D4 1D6 2D0 2D2 2D4 2D7 3D0 3D2 3D4 3D6 4D0 4D2 4D4 4D7
1Q0 1Q2 1Q4 1Q6 2Q0 2Q2 2Q4 2Q7 3Q0 3Q2 3Q4 3Q6 4Q0 4Q2 4Q4 4Q7
1Q1 1Q3 1Q5 1Q7 2Q1 2Q3 2Q5 2Q6 3Q1 3Q3 3Q5 3Q7 4Q1 4Q3 4Q5 4Q6
1CP 2CP 3CPGND GND GND GND 4CP
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
GND GND GND GND
1OE
6
5
2
1
4
3 2OE 3OEGND GND GND GND 4OEGND GND GND GND
AHJBDEG TCF KMNRLP
Table 2. Pin description
Symbol Ball Description
nOE
(n = 1 to 4) A3, H3, J3, T3 output enable input (active LOW)
nCP (n = 1 to 4) A4, H4, J4, T4 clock input
1D[0:7] A5, A6, B5, B6, C5, C6, D5, D6 data input
2D[0:7] E5, E6, F5, F6, G5, G6, H6, H5 data input
3D[0:7] J5, J6, K5, K6, L5, L6, M5, M6 data input
4D[0:7] N5, N6, P5, P6, R5, R6, T6, T5 data input
1Q[0:7] A2, A1, B2, B1, C2, C1, D2, D1 data output
2Q[0:7] E2, E1, F2, F1, G2, G1, H1, H2 data output
3Q[0:7] J2, J1, K2, K1, L2, L1, M2, M1 data output
4Q[0:7] N2, N1, P2, P1, R2, R1, T1, T2 data output
GND B3, B4, D3, D4, E3, E4, G3, G4, K3, K4, M3,
M4, N3, N4, R3, R4
ground (0 V)
V
CC
C3, C4, F3, F4, L3, L4, P3, P4 supply voltage
P1-P3P4-P6P7-P9P10-P12P13-P15

74LVCH32374AEC,551

Mfr. #:
Buy 74LVCH32374AEC,551
Manufacturer:
NXP Semiconductors
Description:
Flip Flops 32-BIT 5V TOLERANT
Lifecycle:
New from this manufacturer.
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