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HTF18C64_128_256x72.fm - Rev. E 3/07 EN
9 ©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
I
DD
Specifications
Table 11: DDR2 IDD Specifications and Conditions – 1GB
Values shown for MT47H128M4 DDR2 SDRAM only and are computed from values specified in the
512Mb (128 Meg x 4) component data sheet
Parameter/Condition Symbol
-80E/
-800
-667 -53E -40E Units
Operating one bank active-precharge current:
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RAS =
t
RAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
IDD0 1,800 1,620 1,440 1,440 mA
Operating one bank active-read-precharge current: I
OUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RAS =
t
RAS MIN
(IDD),
t
RCD =
t
RCD (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data pattern is same as I
DD4W
I
DD1 2,070 1,890 1,710 1,620 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
I
DD2P 126 126 126 126 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
IDD2Q 900 810 720 630 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
IDD2N 990 900 810 720 mA
Active power-down current: All device banks open;
t
CK =
t
CK (IDD); CKE is LOW; Other control and address bus
inputs are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
DD3P 720 630 540 450 mA
Slow PDN exit
MR[12] = 1
216 216 216 216 mA
Active standby current: All device banks open;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Other control and address bus inputs are switching; Data bus
inputs are switching
I
DD3N 1,260 1,170 990 810 mA
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
I
DD4W 3,510 3,060 2,520 2,070 mA
Operating burst read current: All device banks open; Continuous burst
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
I
DD4R 3,690 3,240 2,610 2,070 mA
Burst refresh current:
t
CK =
t
CK (IDD); REFRESH command at every
t
RFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other
control and address bus inputs are switching; Data bus inputs are switching
I
DD5 4,140 3,240 3,060 2,970 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
I
DD6 126 126 126 126 mA
Operating bank interleave read current: All device banks interleaving
reads; I
OUT = 0mA; BL = 4, CL = CL (IDD), AL =
t
RCD (IDD) - 1 x
t
CK (IDD);
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RRD =
t
RRD (IDD),
t
RCD =
t
RCD (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
I
DD7 5,400 4,320 4,050 3,960 mA
