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ADP3334ARMZ-REEL

P1-P3P4-P6P7-P9P10-P12
REV.
ADP3334
–9–
3. The solder mask opening should be about 120 microns
(4.7 mils) larger than the pad size resulting in a minimum
60 micron (2.4 mils) clearance between the pad and the
solder mask.
4. The paste mask opening is typically designed to match the
pad size used on the peripheral pads of the LFCSP package.
This should provide a reliable solder joint as long as the
stencil thickness is about 0.125 mm.
The paste mask for the thermal pad needs to be designed for
the maximum coverage to effectively remove the heat from the
package. However, due to the presence of thermal vias and the
size of the thermal pad, eliminating voids may not be possible.
5. The recommended paste mask stencil thickness is 0.125 mm.
A laser cut stainless steel stencil with trapezoidal walls should
be used.
A “No Clean” Type 3 solder paste should be used for mount-
ing the LFCSP package. Also, a nitrogen purge during the
reflow process is recommended.
6. The package manufacturer recommends that the reflow
temperature should not exceed 220°C and the time above
liquidus is less than 75 seconds. The preheat ramp should be
3°C/second or lower. The actual temperature profile depends
on the board density and must determined by the assembly
house as to what works best.
Use the following general guidelines when designing printed
circuit boards.
1. Keep the output capacitor as close as possible to the out-
put and ground pins.
2. Keep the input capacitor as close as possible to the input
and ground pins.
3. PC board traces with larger cross sectional areas will remove
more heat from the ADP3334. For optimum heat transfer,
specify thick copper and use wide traces.
4. Use additional copper layers or planes to reduce the
thermal resistance. When connecting to other layers, use
multiple vias if possible.
Shutdown Mode
Applying a TTL high signal to the shutdown (SD) pin or the
input pin will turn the output off. Pulling SD down to 0.4 V or
below or tying it to ground will turn the output on. In shutdown
mode, quiescent current is reduced to much less than 1 µA.
ADP3334 Data Sheet
Rev. C | Page 10
OUTLINE DIMENSIONS
Figure 7. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Figure 8. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Data Sheet ADP3334
Rev. C | Page 11
Figure 9. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Package Description Package Option Branding
ADP3334ARZ 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADP3334ARZ-REEL 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADP3334ARZ-REEL7 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADP3334ACPZ-REEL7 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-8-13
LLA
ADP3334ARMZ-REEL7 8-Lead Mini Small Outline Package [MSOP] RM-8 L1N
1
Z = RoHS Compliant Part.
REVISION HISTORY
1/14—Rev. B to Rev. C
Added EPAD Note ............................................................................ 3
Changes to Figure 9, Outline Dimensions .................................. 10
Changes to Ordering Guide .......................................................... 11
3/03—Rev. A to Rev. B
Edits to Specifications ...................................................................... 2
Edits to Output Voltage ................................................................... 6
Added text to Output Voltage section ........................................... 7
Added Figure 4 .................................................................................. 7
Edits to Calculating Junction Temperature section ..................... 8
Renumbered Figures 5 and 6 .......................................................... 8
1/03—Rev. 0 to Rev. A
Added 8-Lead LFCSP and 8-Lead MSOP Package ........ Universal
Edits to product title ......................................................................... 1
Edits to Features ................................................................................. 1
Edits to Applications ......................................................................... 1
Edits to General Description ........................................................... 1
Removed pin numbers from Figure 1 ............................................. 1
Edits to Specifications ....................................................................... 2
Edits to Absolute Maximum Ratings .............................................. 3
Edits to Ordering Guide ................................................................... 3
Added pinouts to Pin Configurations ............................................ 3
Added text to Calculating Junction Temperature section ........... 8
Added LFCSP Layout Considerations section .............................. 8
Added Figure 5 .................................................................................. 8
Updated 8-Lead SOIC Package ..................................................... 10
TOP VIEW
8
1
5
4
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.55
1.45
1.35
1.84
1.74
1.64
0.203 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS MO-229-WEED
12-07-2010-A
P
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1
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R
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1
5
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©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02610-0-1/14(C)
P1-P3P4-P6P7-P9P10-P12

ADP3334ARMZ-REEL

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Manufacturer:
Analog Devices Inc.
Description:
IC REG LIN POS ADJ 500MA 8MSOP
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