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ADP3334ARMZ-REEL

P1-P3P4-P6P7-P9P10-P12
REV. –6–
ADP3334
THEORY OF OPERATION
The new anyCAP
LDO ADP3334 uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2 that is
varied to provide the available output voltage option. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
PTAT
V
OS
NONINVERTING
WIDEBAND
DRIVER
INPUT
Q1
ADP3334
COMPENSATION
CAPACITOR
ATTENUATION
(V
BANDGAP
/V
OUT
)
R1
D1
R2
R3
R4
OUTPUT
PTAT
CURRENT
(a)
C
LOAD
R
LOAD
FB
GND
g
m
Figure 2. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that equilibrium pro-
duces a large, temperature-proportional input, “offset voltage”
that is repeatable and very well controlled. The temperature-
proportional offset voltage is combined with the complementary
diode voltage to form a “virtual band gap” voltage, implicit in
the network although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control
the loop with only one amplifier. This technique also improves
the noise characteristics of the amplifier by providing more
flexibility on the trade-off of noise sources that leads to a low
noise design.
The R1, R2 divider is chosen in the same ratio as the band gap
voltage to the output voltage. Although the R1, R2 resistor divider
is loaded by the diode D1 and a second divider consisting of R3
and R4, the values can be chosen to produce a temperature stable
output. This unique arrangement specifically corrects for the
loading of the divider, thus avoiding the error resulting from
base current loading in conventional circuits.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole-splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitance.
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to stabilize
due to the uncertainty of load capacitance and resistance. More-
over, the ESR value, required to keep conventional LDOs stable,
changes depending on load and temperature. These ESR limita-
tions make designing with LDOs more difficult because of their
unclear specifications and extreme variations over temperature.
With the ADP3334 anyCAP LDO, this is no longer true. It can
be used with virtually any good quality capacitor, with no con-
straint on the minimum ESR. This innovative design allows the
circuit to be stable with just a small 1 mF capacitor on the out-
put. Additional advantages of the pole-splitting scheme include
superior line noise rejection and very high regulator gain, which
lead to excellent line and load regulation. An impressive ±1.8%
accuracy is guaranteed over line, load, and temperature.
Additional features of the circuit include current limit and ther-
mal shutdown.
APPLICATION INFORMATION
Output Capacitor
As with any micropower device, output transient response is a
function of the output capacitance. The ADP3334 is stable with
a wide range of capacitor values, types, and ESR (anyCAP).
A capacitor as low as 1 µF is all that is needed for stability;
larger capacitors can be used if high output current surges are
anticipated. The ADP3334 is stable with extremely low ESR
capacitors (ESR ⬇ 0), such as multilayer ceramic capacitors
(MLCC) or OSCON. Note that the effective capacitance of some
capacitor types may fall below the minimum over the operating
temperature range or with the application of a dc voltage.
Input Bypass Capacitor
An input bypass capacitor is not strictly required but is advisable
in any application involving long input wires or high source
impedance. Connecting a 1 µF capacitor from IN to ground
reduces the circuit’s sensitivity to PC board layout. If a larger
value output capacitor is used, then a larger value input capaci-
tor is also recommended.
Noise Reduction Capacitor
A noise reduction capacitor (C
NR
) can be placed between the
output and the feedback pin to further reduce the noise by
6dB to 10 dB (TPC 18). Low leakage capacitors in the 100 pF
to 1 nF range provide the best performance. Since the feedback
pin (FB) is internally connected to a high impedance node, any
connection to this node should be carefully done to avoid noise
pickup from external sources. The pad connected to this pin
should be as small as possible, and long PC board traces are not
recommended.
When adding a noise reduction capacitor, maintain a mini-
mum load current of 1 mA when not in shutdown.
It is important to note that as C
NR
increases, the turn-on time
will be delayed. With C
NR
values of 1 nF, this delay may be
on the order of several milliseconds.
C
NR
ADP3334
OUT
V
IN
IN
GND
V
OUT
ON
OFF
IN
OUT
R1
R2
SD
C
IN
1F
FB
C
OUT
1F
Figure 3. Typical Application Circuit
Output Voltage
The ADP3334 has an adjustable output voltage that can be set
by an external resistor divider. The output voltage will be divided
by R1 and R2 and then fed back to the FB pin.
C
REV.
ADP3334
–7–
To have the lowest possible sensitivity of the output voltage to
temperature variations, it is important that the value of the parallel
resistance of R1 and R2 be kept as close as possible to 50 kW.
RR
RR
k
12
12
50
¥
+
=W
(1)
Also, for the best accuracy over temperature, the feedback volt-
age should be set for 1.178 V:
VV
R
RR
FB OUT
=¥
+
Ê
Ë
Á
ˆ
¯
˜
2
12
(2)
where V
OUT
is the desired output voltage and V
FB
is the virtual
band gap voltage. Note that V
FB
does not actually appear at the
FB pin due to loading by the internal PTAT current.
Combining the above equations and solving for R1 and R2 gives
the following formulas:
Rk
V
V
OUT
FB
150=¥
Ê
Ë
Á
ˆ
¯
˜
W
(3)
R
k
V
V
FB
OUT
2
50
1
=
-
Ê
Ë
Á
ˆ
¯
˜
W
(4)
Table I. Feedback Resistor Selection
V
OUT
(V) R1 (1% Resistor) (k) R2 (1% Resistor) (k)
1.5 63.4 232.0
1.8 76.8 147.0
2.2 93.1 107.0
2.7 115.0 88.7
3.3 140.0 78.7
5.0 210.0 64.9
10.0 422.0 56.2
Using standard 1% values, as shown in Table I, will sacrifice
some output voltage accuracy. To estimate the overall output
voltage accuracy, it is necessary to take into account all sources
of error. The accuracy given in the specifications table does not
take into account the error introduced by the feedback resistor
divider ratio or the error introduced by the parallel combination
of the feedback resistors.
The error in the parallel combination of the feedback resistors
causes the reference to have a wider variation over temperature.
To estimate the variation, calculate the worst-case error from
50 kW, and then use the graph in Figure 4 to estimate the
additional change in the output voltage over the operating
temperature range.
For example:
V
IN
= 5 V
V
OUT
= 3.3 V
R1 = 140 kW, 1%
R2 = 78.7 kW, 1%
Rp ERROR – %
OUTPUT ERROR – %
3.0
2.5
2.0
1.5
1.0
0.5
0
023456
Figure 4. Output Voltage Error vs.
Parallel Resistance Error
The actual output voltage can be calculated using the following
equation.
V.V
R
R
V.V
OUT
OUT
=¥+
Ê
Ë
Á
ˆ
¯
˜
=
1 178
1
2
1
3 274
(5)
So worst-case error will occur when R1 has a –1% tolerance and
R2 has a +1% tolerance. Recalculating the output voltage, the
parallel resistance and error are:
V.V
.
.
V.V
Resistor Divider Error
.
.
OUT
OUT
=¥+
Ê
Ë
Á
ˆ
¯
˜
=
=-
Ê
Ë
Á
ˆ
¯
˜
¥=-
1 178
138 6
79 5
1
3 232
3 232
33
1 100 2 1%.%
(6)
R
RR
RR
..
..
. k
R Error
.
PARALLEL
PARALLEL
=
¥
+
=
¥
+
=
=-
Ê
Ë
Á
ˆ
¯
˜
¥=
12
12
138 6 79 5
138 6 79 5
50 51
50 51
50
1 100 1 02
W
%.%
(7)
So, from the graph in Figure 4, the output voltage error is
estimated to be an additional 0.25%. The error budget is
1.8% (the initial output voltage accuracy over temperature),
plus 2.1% (resistor divider error), plus 0.25% (parallel resis-
tance error) for a worst-case total of 4.15%.
Thermal Overload Protection
The ADP3334 is protected against damage from excessive power
dissipation by its thermal overload protection circuit, which limits
the die temperature to a maximum of 165°C. Under extreme
conditions (i.e., high ambient temperature and power dissipation)
where die temperature starts to rise above 165°C, the output
current is reduced until the die temperature has dropped to a safe
level. The output current is restored when the die temperature
is reduced.
REV. –8–
ADP3334
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation should be externally limited
so that junction temperatures will not exceed 150°C.
Calculating Junction Temperature
Device power dissipation is calculated as follows:
PVV I VI
DINOUT LOAD IN GND
=-
()
+
()
(8)
where I
LOAD
and I
GND
are load current and ground current, V
IN
and V
OUT
are input and output voltages, respectively.
Assuming I
LOAD
= 400 mA, I
GND
= 4 mA, V
IN
= 5.0 V and
V
OUT
= 2.8 V, device power dissipation is:
PmAmAmW
D
=-
()
+
()
=528400 5 0 4 900..
(9)
As an example, the proprietary package used in the ADP3334
has a thermal resistance of 86.6°C/W, significantly lower than
a standard SOIC-8 package. Assuming a 4-layer board, the
junction temperature rise above ambient temperature will be
approximately equal to:
DT=. W CW C
A
J
0 900 86 6 77 9¥ ∞ = ∞./ .
(10)
To limit the maximum junction temperature to 150°C, maxi-
mum allowable ambient temperature will be:
TC/WC
AMAX
= ∞ - ∞ = ∞150 77 9 72 1C ..
(11)
The maximum power dissipation versus ambient temperature
for each package is shown in Figure 5.
AMBIENT TEMPERATURE – C
3.5
–20 0 20 406080
POWER DISSIPATION – W
2.5
1.5
1.0
0.5
0
3.0
2.0
158C/W MSOP
220C/W MSOP
122C/W SOIC
86C/W SOIC
62C/W LFCSP
48C/W LFCSP
Figure 5. Power Derating Curve
Printed Circuit Board Layout Consideration
All surface-mount packages rely on the traces of the PC board
to conduct heat away from the package.
In standard packages, the dominant component of the heat
resistance path is the plastic between the die attach pad and the
individual leads. In typical thermally enhanced packages, one or
more of the leads are fused to the die attach pad, significantly
decreasing this component. To make the improvement mean-
ingful, however, a significant copper area on the PCB must be
attached to these fused pins.
As an example, the patented thermal coastline lead frame design
of the ADP3334 uniformly minimizes the value of the dominant
portion of the thermal resistance. It ensures that heat is con-
ducted away by all pins of the package. This yields a very low
86.6°C/W thermal resistance for the SOIC-8 package, without
any special board layout requirements, relying only on the normal
traces connected to the leads. This yields a 15% improvement in
heat dissipation capability as compared to a standard SOIC-8
package. The thermal resistance can be decreased by an addi-
tional 10% by attaching a few square centimeters of copper area
to the IN or OUT pins of the ADP3334 package.
It is not recommended to use solder mask or silkscreen on the
PCB traces adjacent to the ADP3334’s pins since it will increase
the junction-to-ambient thermal resistance of the package.
0.50
2x VIAS, 0.250
35µm PLATING
3.36
0.90
1.80
2.36
1.90
1.40
0.30
0.73
Figure 6. 3 mm x 3 mm LFCSP Pad Pattern
(Dimensions shown in millimeters)
LFCSP Layout Considerations
The LFCSP package has an exposed die paddle on the bottom,
which efficiently conducts heat to the PCB. In order to achieve
the optimum performance from the LFCSP package, special
consideration must be given to the layout of the PCB. Use the
following layout guidelines for the LFCSP package.
1. The pad pattern is given in Figure 6. The pad dimension
should be followed closely for reliable solder joints while
maintaining reasonable clearances to prevent solder bridging.
2. The thermal pad of the LFCSP package provides a low ther-
mal impedance path (approximately 20°C/W) to the PCB.
Therefore the PCB must be properly designed to effectively
conduct the heat away from the package. This is achieved by
adding thermal vias to the PCB, which provide a thermal
path to the inner or bottom layers. See Figure 5 for the rec-
ommended via pattern. Note that the via diameter is small to
prevent the solder from flowing through the via and leaving
voids in the thermal pad solder joint.
Note that the thermal pad is attached to the die substrate, so
the thermal planes that the vias attach the package to must
be electrically isolated or connected to V
IN
. Do NOT con-
nect the thermal pad to ground.
C
P1-P3P4-P6P7-P9P10-P12

ADP3334ARMZ-REEL

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Manufacturer:
Analog Devices Inc.
Description:
IC REG LIN POS ADJ 500MA 8MSOP
Lifecycle:
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