9DB433
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
IDT®
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3 10
9DB433 REV H 06/07/16
General SMBus Serial Interface Information for 9DB433
How to Write
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
*Assuming SMB_ADR_tri is at mid-level
How to Read
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X
(H)
was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
O O
O O
O
Byte N + X - 1
ACK
PstoP bit
Read Address Write Address
DD*
(H)
DC*
(H)
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
O O
O O
O
Byte N + X - 1
N Not acknowledge
PstoP bit
9DB433
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
IDT®
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3 11
9DB433 REV H 06/07/16
SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (Selectable)
Pin # Name Control Function T
yp
e0 1Default
Bit 7
PD_Mode PD# drive mode RW driven Hi-Z 1
Bit 6
OE_Mode OE#_Stop drive mode RW driven Hi-Z 0
Bit 5
0
Bit 4
X
Bit 3
MODE1 BYPASS#/PLL1 RW Latched
Bit 2
1
Bit 1
MODE0 BYPASS#/PLL0 RW Latched
Bit 0
SRC_DIV# SRC Divide by 2 Select RW x/2 x/1 1
SMBus Table: Output Control Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7
1
Bit 6
DIF_6 Output Enable RW Disable Enable 1
Bit 5
DIF_5 Output Enable RW Disable Enable 1
Bit 4
1
Bit 3
1
Bit 2
DIF_2 Output Enable RW Disable Enable 1
Bit 1
DIF_1 Output Enable RW Disable Enable 1
Bit 0
1
NOTE:
The SMBus Output Enable Bit must be '1' AND the respective OE pin must be active for the output to run!
SMBus Table: OE Pin Control Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7
0
Bit 6
DIF_6 DIF_6 Stoppable with OE6# RW Free-run Stoppable 0
Bit 5
DIF_5 DIF_5 Stoppable with OE5# RW Free-run Stoppable 0
Bit 4
0
Bit 3
0
Bit 2
DIF_2 DIF_2 Stoppable with OE2# RW Free-run Stoppable 0
Bit 1
DIF_1 DIF_1 Stoppable with OE1# RW Free-run Stoppable 0
Bit 0
0
SMBus Table: Reserved Register
Pin # Name Control Function T
yp
e0 1Default
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6,7
Reserved
B
y
te 3
Reserved
Reserved
Reserved
NOTE:
Only OE1# and OE6# are available on 28-TSSOP/SSOP packages. If you wish the default to be "Stoppable" see the 9DB434.
19,20
9,10
Reserved
6,7
22,23
B
y
te 1
9,10
B
y
te 2
B
y
te 0
-
-
-
-
-
Reserved
22,23
19,20
-
-
-
See Operating Mode
Readback Table
See Operating Mode
Readback Table
Reserved
Reserved
9DB433
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
IDT®
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3 12
9DB433 REV H 06/07/16
SMBus Table: Vendor & Revision ID Register
Pin # Name Control Function T
yp
e0 1Defaul
t
Bit 7
RID3 R - - 0
Bit 6
RID2 R - - 0
Bit 5
RID1 R - - 0
Bit 4
RID0 R - -
1
Bit 3
VID3 R - - 0
Bit 2
VID2 R - - 0
Bit 1
VID1 R - - 0
Bit 0
VID0 R - - 1
SMBus Table: DEVICE ID
Pin # Name Control Function T
yp
e0 1Defaul
t
Bit 7
DID7 Device ID 7 (MSB) R 0
Bit 6
DID6 Device ID 6 R 1
Bit 5
DID5 Device ID 5 R 0
Bit 4
DID4 Device ID 4 R 0
Bit 3
DID3 Device ID 3 R 0
Bit 2
DID2 Device ID 2 R 0
Bit 1
DID1 Device ID 1 R 1
Bit 0
DID0 Device ID 0 R 1
SMBus Table: Byte Count Register
Pin # Name Control Function T
yp
e0 1Defaul
t
Bit 7
BC7 RW - - 0
Bit 6
BC6 RW - - 0
Bit 5
BC5 RW - - 0
Bit 4
BC4 RW - - 0
Bit 3
BC3 RW - - 0
Bit 2
BC2 RW - - 1
Bit 1
BC1 RW - - 1
Bit 0
BC0 RW - - 1
-
Device ID is 43 Hex for
9DB433
-
-
-
-
B
y
te 6
-
Writing to this register configures how
many bytes will be read back.
-
-
-
-
-
-
-
B
y
te 5
-
-
-
-
-
VENDOR ID
-
-
-
B
y
te 4
-
REVISION ID
-
-

9DB433AFILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 4 OUTPUT PCIE GEN3 BUFFER
Lifecycle:
New from this manufacturer.
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