9DB433AFILF Datasheet 9DB433AGILF, 9DB433AGILFT, 9DB433AFLFT | P7-P9

9DB433

FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3

IDT®

FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3 7

9DB433 REV H 06/07/16

Electrical Characteristics–PCIe Phase Jitter Parameters

Clock Periods–Differential Outputs Tracking Spread Spectrum

TA = T

COM

or T

IND;

Supply Voltage VDD = 3.3 V +/-5%

PARAMETER SYMBOL CONDITIONS MIN TYP MAX

INDUSTRY

LIMIT

UNITS Notes

jphPCIeG1

PCIe Gen 1 26 40 86

(p-p)

1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.8 1.2 3

(rms)

1,2

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

1.6

1.8 3.1

(rms)

1,2

jphPCIeG3

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)

0.48

0.6 1

(rms)

1,2,4

jphPCIeG1

PCIe Gen 1 2.6 5 N/A ps (p-p) 1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.06 0.2 N/A

(rms)

1,2

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

0.3 N/A

(rms)

1,2

jphPCIeG3

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)

0.1 N/A

(rms)

1,2

Applies to all outputs.

jphPCIeG2

See http://www.pcisig.com for complete specs

jphPCIeG2

Phase Jitter, PLL Mode

Additive Phase Jitter,

Bypass Mode

Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.

1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock

Lg- -SSC -ppm error 0ppm

m error

+SSC Lg+

Absolute

Period

Short-term

Average

Long-Term

Average

Period

Long-Term

Average

Short-term

Average

Period

Minimum

Absolute

Period

Minimum

Absolute

Period

Minimum

Absolute

Period

Nominal Maximum Maximum Maximum

9.949 9.999 10.024 10.025 10.026 10.051 10.101

ns 1,2,3

Symbol

DIF 100

Notes

Definition

Units

Measurement

Window

9DB433

FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3

IDT®

FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3 8

9DB433 REV H 06/07/16

Common Recommendations for Differential Routing Dimension or Value Unit Figure

L1 length, route as non-coupled 50ohm trace 0.5 max inch 1

L2 length, route as non-coupled 50ohm trace 0.2 max inch 1

L3 length, route as non-coupled 50ohm trace 0.2 max inch 1

Rs 33 ohm 1

Rt 49.9 ohm 1

Down Device Differential Routing

L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1

L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1

Differential Routing to PCI Express Connector

L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2

L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2

Output Termination and Layout Information

HCSL Output Buffer

L1'

L2'

L4'

L3L3'

Rt Rt

PCI Express

Down Device

REF_CLK Input

Figure 1: Down Device Routing

HCSL Output Buffer

L1'

L2'

L4'

L3L3'

Rt Rt

PCI Express

Add-in Board

REF_CLK Input

Figure 2: Differential Routing to PCI Express Controller

9DB433

FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3

IDT®

FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3 9

9DB433 REV H 06/07/16

Vdiff Vp-p Vcm R1 R2 R3 R4 Note

0.45v 0.22v 1.08 33 150 100 100

0.58 0.28 0.6 33 78.7 137 100

0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible

0.60 0.3 1.2 33 174 140 100 Standard LVDS

R1a = R1b = R1

R2a = R2b = R2

Termination for LVDS and other Common Differential Signals (figure 3)

HCSL Output Buffer

L1'

R1b

L2'

R1a

L4'

R2a R2b

Down Device

REF_CLK Input

Figure 3

L3'

R3 R4

Component Value Note

R5a, R5b 8.2K 5%

R6a, R6b 1K 5%

Cc 0.1 µF

Vcm 0.350 volts

Termination for Cable AC Coupled Application (figure 4)

PCIe Device

REF_CLK Input

Figure 4

R5a

L4'

3.3 Volts

R5b

R6a R6b

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

9DB433AFILF

Mfr. #:

Buy 9DB433AFILF

Manufacturer:

IDT

Description:

Clock Buffer 4 OUTPUT PCIE GEN3 BUFFER

Lifecycle:

New from this manufacturer.

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9DB433AFILF

9DB433AFILF

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