9DB433
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
IDT®
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3 16
9DB433 REV H 06/07/16
Revision History
Rev. Issue Date Who Description Page #
A 6/30/2010 RDW Released to final
B 5/9/2011 RDW
1. Update pin 1 pin-name and pin description from VDD to VDDR. This
highlights that optimal peformance is obtained by treating VDDR as in
analog pin. This is a document update only, there is no silicon change. Various
C 3/13/2012 RDW
1. Added additional line to PLL Bandwidth "-3dB point in High BW Mode"
conditions for industrial mode (min1.5, typ 2.7, max 4.1 MHz)
2. Added additional line to Skew, Input to Output "Bypass Mode"
conditions for industrial mode (min 2500, max 4900 ps)
6
D 7/5/2012 RDW 1. Changed references of PCIe Gen3 to PCIe Gen1,2,3 1
E 7/12/2012 RDW 1. Added missing typical values to DS. Various
F 9/18/2012 RDW
Updated Byte 2, bits 1, 2, 5 and 6 per char review. Outputs can be
programmed with Byte 2 to be Stoppable or Free-Run with DIF_Stop pin,
not the OE pins.
Various
F 9/30/2013 RDW Corrected typo in ordering information for 28-SSOP I-temp device. 15
G 8/14/2015 RDW
1. Corrected default value of Byte 2 to 00hex. Added note referring to
9DB434 if FFhex is the desired default.
11
H 6/7/2016 RDW
1. Corrected Idd values for 9DB433.
2. Updated typical values in electrical tables.
3. Updated clock input electrical table to latest format.
4. Updated SMbus operating frequency to 440KHz.
5. Corrected typo in Byte 0, bit 6 defaults to 0.
Various
