P1P3800AG12CRTWG Datasheet P1P3800AG12CRTWG | P1-P3

January, 2012 − Rev. 1

1 Publication Order Number:

P1P3800A/D

P1P3800A

Phase Synchronizing Clock

Generator

Product Description

P1P3800A is a Phase Synchronizing clock generator that generates

four outputs from an input clock. Output frequency will be a divide by

two of the input clock. The phase of the output clocks is selectable

through four select signals S1, S2, S3 and S4. Refer to Output Clock

Selection Table. The outputs will go ‘low’ when all the select signals

are ‘low’. The transition to a new state of the output will be ‘glitch

free’ when the select inputs change state. A Power Down signal

enables the device to be driven to a power save mode, when active.

The device works over a supply voltage range of 3.8 V − 5.5 V. The

device is available in a 12−Lead 3mmx3mm WQFN package and

operates over -40°C to +85°C.

Features

• Input Clock Frequency:

120 Hz − 240 Hz (External Reference Clock)

• Output Clock Frequency:

60 Hz − 120 Hz

• 4 Clock Outputs

• 4 Two Level Controls to Select Sets of Clock Outputs

• Output Buffer Drive Strength: 8 mA

• Supply Voltage: 3.8 V − 5.5 V

• Power Down for Power Save

• 12−Lead 3mmx3mm WQFN Package

• Operating Temperature Range: -40°C to +85°C

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Application

• P1P3800A can be used in applications where Phase Synchronization

is needed.

GND

CLKIN

Digital Logic

& Divider

S [1:4] PD#

CLKOUT [1:4]

Figure 1. Block Diagram

WQFN12

CASE 510AH

MARKING

DIAGRAM

http://onsemi.com

PD#

CLKOUT4

CLKOUT3

CLKIN

PIN CONFIGURATION

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

ORDERING INFORMATION

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G = Pb−Free Package

P1P

3800A

ALYWG

12 11 10

CLKOUT2

GND

CLKOUT1

(Note: Microdot may be in either location)

P1P3800A

(Top−View)

P1P3800A

http://onsemi.com

Table 1. PIN DESCRIPTION

Pin# Pin Name Type Description

1 S2 I Output clock select. Refer Output Clock selection table. Has NO default state

2 S1 I Output clock select. Refer Output Clock selection table. Has NO default state.

3 CLKIN I External Reference Clock Input

4 S3 I Output clock select. Refer Output Clock selection table. Has NO default state.

5 GND P Ground to entire chip

6 S4 I Output clock select. Refer Output Clock selection table. Has NO default state.

7 CLKOUT3 O Buffered clock output. Refer CLKOUT Diagram

8 CLKOUT4 O Buffered clock output. Refer CLKOUT Diagram

9 PD# I Power Down. Powers down the entire chip when pulled LOW. CLKOUT [1:4] will be LOW

when power down is enabled. Has NO default state.

10 CLKOUT2 O Buffered clock output. Refer CLKOUT Diagram

11 V

P Supply Voltage

12 CLKOUT1 O Buffered clock output. Refer CLKOUT Diagram

Table 2. OUTPUT CLOCK SELECTION TABLE

S4 S3 S2 S1 CLKOUT4 CLKOUT3 CLKOUT2 CLKOUT1

0 0 0 0 Low Low Low Low

0 0 0 1 CLK# CLK# CLK# CLK

0 0 1 0 CLK# CLK# CLK CLK#

0 0 1 1 CLK# CLK# CLK CLK

0 1 0 0 CLK# CLK CLK# CLK#

0 1 0 1 CLK# CLK CLK# CLK

0 1 1 0 CLK# CLK CLK CLK#

0 1 1 1 CLK# CLK CLK CLK

1 0 0 0 CLK CLK# CLK# CLK#

1 0 0 1 CLK CLK# CLK# CLK

1 0 1 0 CLK CLK# CLK CLK#

1 0 1 1 CLK CLK# CLK CLK

1 1 0 0 CLK CLK CLK# CLK#

1 1 0 1 CLK CLK CLK# CLK

1 1 1 0 CLK CLK CLK CLK#

1 1 1 1 CLK CLK CLK CLK

P1P3800A

http://onsemi.com

CLKOUT Diagram

LOWCLK#CLK

TIMING Diagram For Glitch Free Operation (For Reference)

(Transition of outputs from any state to any other state)

S4=1, S3=1, S2=1, S1=0 Change Area S4=1, S3=1, S2=0, S1=1 Change Area S4=0, S3=0, S2=1, S1=1

PD#

PD#=0

Latency Latency

Input

Clock

CLKOUT1

CLKOUT2

CLKOUT3

CLKOUT4

Note: Transition to new state will happen after a latency of one output clock cycle after completing the present output clock cycle

Transition to new state will happen after a latency of up to 3 input clock cycles excluding the input cycle where the transition has

occured.

Power Up

CLKOUT

I/P CLK

S1~S4 in any stable

state

Valid Clock according to S1~S4

10mS(min)

Note: Transition to new state will happen after a latency of up to 2 input clock cycles excluding the input cycle where the transition has

occured.

P1-P3 P4-P6 P7-P7

P1P3800AG12CRTWG

Mfr. #:

Buy P1P3800AG12CRTWG

Manufacturer:

ON Semiconductor

Description:

Clock Generators & Support Products PHASE SYNCHRONIZING CLOCK

Lifecycle:

New from this manufacturer.

Delivery:

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P1P3800AG12CRTWG