M2020/21 Datasheet Rev 1.1 3 of 10 Revised 20Jul2009
Integrated Circuit Systems, Inc.
●
Networking & Communications
●
www.icst.com
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tel (508) 852-5400
M2020/21
VCSO B
ASED
C
LOCK
PLL
Product Data Sheet
Integrated
Circuit
Systems, Inc.
D
ETAILED
B
LOCK
D
IAGRAM
Figure 3: Detailed Block Diagram
D
IVIDER
S
ELECTION
T
ABLES
Mfin Divider Look-Up Table (LUT)
The
FIN_SEL1:0
pins select the Mfin divider value, which
establishes the PLL clock multiplication ratio. Since the
VCSO frequency is fixed, this allows input reference
selection.
M and R Divider Look-Up Table (LUT)
The
MR_SEL1:0
pins select the M and R divider values,
which establish phase detector frequency. A lower
phase detector frequency improves jitter tolerance and
lowers loop bandwidth.
P Divider Look-Up Table (LUT)
The
P_SEL2:0
pins select the P divider values, which set
the output clock frequencies. A P divider of value of
1
will provide a
622.08MHz
output when using a
622.08MHz
VCSO, for example. P divider values of
4
,
8
, or
32
are
also available, plus a TriState mode. The outputs can
be placed into the valid state combinations as listed in
Table 5. (The outputs cannot each be placed
into any of
the five available states independently.)
General Guidelines for M and R Divider Selection
•
A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is
19.44MHz
.
•
When
LOL
is to be used for system health monitoring,
the phase detector frequency should be 5MHz or
greater. Low phase detector frequencies make
LOL
overly sensitive, and higher phase detector
frequencies make
LOL
less sensitive. The
LOL
pin
should not be used during loop timing mode.
Mfin Divider
LUT
Phase
Locked
Loop
(PLL)
M2020/21
SAW Delay Line
Phase
Shifter
VCSO
C
POS
T
C
POS
T
VCnVC
R
POS
T
nOP_OUTOP_OUT
R
POS
T
R
LOOP
R
LOOP
C
LOOP
C
LOOP
OP_IN nOP_IN
Phase
Detector
Loop Filter
Amplifier
External
Loop Filter
Components
MR_SEL1:0
FIN_SEL1:0
MUX
0
REF_SEL
DIF_REF0
nDIF_REF0
1
P_SEL2:0
R
IN
DIF_REF1
nDIF_REF1
LOL
R Div
(1, 4,
16, 64)
P Divider
LUT
P Divider
(for FOUT0: 1, 4, 8, or 32),
(for FOUT1: 1, 4, or 8)
M and R Divider
LUT
NB
W
M Div
(1, 4, 16, 64)
Mfin Divider
(1, 4, 8, 32 or
1, 4, 8, 16)
FOUT0
nFOUT0
TriState
FOUT1
nFOUT1
2
2
3
Hitless Switching (HS) Opt.
HS with Phase Build-out Opt.
FIN_SEL1:0
Mfin Value
Input Ref. Freq. (MHz)
1
M2020-yz-622.0800 or M2021-yz-622.0800
Note 1: Example with
M2020-yz-622.0800 or M2021-yz-622.0800
00
(M2020) (M2021)
32 or 16 19.44 or 38.88
0 1 8 77.76
1 0 4 155.52
1 1 1 622.08
Table 3: Mfin Divider Look-Up Table (LUT)
MR_SEL1:0
M R Description
0 0
1
Note 1: Do not use with FIN_SEL1:0=11; Maximum Phase Detector
Frequency=175MHz
11
Four sets of divider values to enable
adjustment of bandwidth and jitter
tolerance
0 1 4 4
1 0 16 16
1 1 64 64
Table 4: M and R Divider Look-Up Table (LUT)
P_SEL2:0
P Value
M2020-yz-622.0800 or M2021-yz-622.0800
Output Frequency (MHz)
FOUT0
FOUT1
for
FOUT0
for
FOUT1
0 0 0
32 1 19.44 622.08
0 0 1
32 4 19.44 155.52
0 1 0 1 1 622.08 622.08
0 1 1 4 1 155.52 622.08
1 0 0 8 8 77.76 77.76
1 0 1
4 4 155.52 155.52
1 1 0
8 4 77.76 155.52
1 1 1 TriState TriState
N/A N/A
Table 5: P Divider Look-Up Table (LUT)
