M2020-13-622.0800 Datasheet M2020-13-622.0800, M2020-11-625.0000, M2020-11-669.3266 | P7-P9

M2020/21 Datasheet Rev 1.1 7 of 10 Revised 20Jul2009

Integrated Circuit Systems, Inc.

●

Networking & Communications

●

www.icst.com

●

tel (508) 852-5400

M2020/21

VCSO B

ASED

C

LOCK

PLL

Product Data Sheet

Integrated

Circuit

Systems, Inc.

PLL Simulator Tool Available

A free PC software utility is available on the ICS website

(www.icst.com). The M2000 Timing Modules PLL

Simulator is a downloadable application that simulates

PLL jitter and wander transfer characteristics. This

enables the user to set appropriate external loop

component values in a given application.

Refer to the M2020/21 product web page at

www.icst.com/products/summary/m2020-2021.htm

for additional product information.

Example Values for Loop Filter External Components

1

for M2020-yz-622.0800 and

M2021-yz-622.0800

VCSO Parameters: K

VCO

= 800kHz/V, R

IN

= 100k

Ω

(pin NBW = 0), VCSO Bandwidth = 700kHz.

Purpose Device Configuration Example External Component Values Nominal Performance With These Values

F

Ref

(MHz)

F

VCSO

(MHz)

FIN_SEL

1:0

MRSEL

1:0

R loop C loop R post C post PLL Loop

Bandwidth

Damping

Factor

Passband

Peaking

(dB)

Frequency

Translation,

General

Usage

155.52 622.08 1 0 0 1

11.5

kΩ

2.2

µF

32.4

kΩ

470

p

1k

Hz

6.0 0.05

77.76 622.08 0 1 0 1

23.2

kΩ

1.0

µF

32.4

kΩ

470

p

1k

Hz

6.5 0.06

38.88

2

622.08 0 0

2

0 0

11.5

kΩ

2.2

µF

32.4

kΩ

470

p

1k

Hz

6.7 0.05

19.44

3

622.08 0 0

3

0 0

23.2

kΩ

1.0

µF

32.4

kΩ

470

p

1k

Hz

6.5 0.06

Jitter

Attenuation,

Narrow

Bandwidth

622.08 622.08 1 1 1 0

5.6

kΩ

10

µF

68

kΩ

470

p

500

Hz

6.3 0.05

77.76 622.08 0 1 0 1

8.2

kΩ

10

µF

100

kΩ

470

p

360

Hz

6.5 0.05

38.88

2

622.08 0 0

2

0 1

12.0

kΩ

10

µF

100

kΩ

470

p

260

Hz

6.7 0.05

19.44

3

622.08 0 0

3

0 0

8.2

kΩ

10

µF

100

kΩ

470

p

360

Hz

6.5 0.05

Table 7: Example Values for Loop Filter External Components

Note 1: K

VCO

, VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor,

and Passband Peaking. For PLL Simulator software, go to www.icst.com.

Note 2: M2021 only.

Note 3: M2020 only.

A

BSOLUTE

M

AXIMUM

R

ATINGS

1

Symbol Parameter Rating Unit

V

I

Inputs -

0.5

to V

CC

+

0.5

V

O

Outputs -

0.5

to V

CC

+

0.5

V

CC

Power Supply Voltage

4.6

V

T

S

Storage Temperature -

45

to +

100

o

C

Table 8: Absolute Maximum Ratings

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional operation of product at these conditions

or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or

AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods

may affect product reliability

.

R

ECOMMENDED

C

ONDITIONS

OF

O

PERATION

Symbol Parameter Min Typ Max Unit

V

CC

Positive Supply Voltage

3.135 3.3 3.465

V

T

A

Ambient Operating Temperature

Commercial

0

+

70

o

C

Industrial

-40

+

85

o

C

Table 9: Recommended Conditions of Operation

M2020/21 Datasheet Rev 1.1 8 of 10 Revised 20Jul2009

Integrated Circuit Systems, Inc.

●

Networking & Communications

●

www.icst.com

●

tel (508) 852-5400

Integrated

Circuit

Systems, Inc.

M2020/21

VCSO B

ASED

C

LOCK

PLL

Product Data Sheet

E

LECTRICAL

S

PECIFICATIONS

DC Characteristics

Unless stated otherwise, V

CC

=

3.3

V +

5

%,T

A

=

0

o

C

to +

70

o

C (commercial), T

A

=

-40

o

C

to +

85

o

C (industrial), F

VCSO

= F

OUT

=

622-675

MHz,

LVPECL outputs terminated with

50

Ω

to V

CC

- 2V

Symbol Parameter Min Typ Max Unit Conditions

Power Supply V

CC

Positive Supply Voltage

3.135 3.3 3.465

V

I

CC

Power Supply Current

175 225

mA

All

Differential

Inputs

V

P

-

P

Peak to Peak Input Voltage

DIF_REF0, nDIF_REF0,

DIF_REF1, nDIF_REF1

0.15

V

CMR

Common Mode Input

0.5 V

cc

-

.85

V

C

IN

Input Capacitance

4

pF

Differential

Inputs with

Pull-down

I

IH

Input High Current

(Pull-down)

DIF_REF0, DIF_REF1

150 µA

V

CC

= V

IN

=

3.456V

I

IL

Input Low Current

(Pull-down)

-

5

µA

R

pulldown

Internal Pull-down Resistance

50

kΩ

Differential

Inputs

Biased to

VCC/2

I

IH

Input High Current

(Biased)

nDIF_REF0, nDIF_REF1

150

µA

V

IN

=

0 to 3.456V

I

IL

Input Low Current

(Biased)

-

150

µA

R

bias

Biased to Vcc/2

See Figure 4

kΩ

All LVCMOS

/ LVTTL

Inputs

V

IH

Input High Voltage

REF_SEL, FIN_SEL1, FIN_SEL0,

MR_SEL1, MR_SEL0, P_SEL2,

P_SEL1, P_SEL0, NBW

2

V

cc

+

0.3

V

IL

Input Low Voltage -

0.3

0.8

V

C

IN

Input Capacitance

4

pF

LVCMOS /

LVT T L

Inputs with

Pull-down

I

IH

Input High Current

(Pull-down)

REF_SEL, FIN_SEL1, FIN_SEL0,

MR_SEL1, MR_SEL0, P_SEL2,

P_SEL1, P_SEL0

150 µA

V

CC

= V

IN

=

3.456V

I

IL

Input Low Current

(Pull-down)

-

5

µA

R

pulldown

Internal Pull-down Resistance

50

kΩ

LVCMOS /

LVT T L

Inputs with

Pull-UP

I

IH

Input High Current

(Pull-UP)

NBW

5 µA

V

CC

= 3.456V

V

IN

= 0 V

I

IL

Input Low Current

(Pull-UP)

-1

50

µA

R

pullup

Internal Pull-UP Resistance

50

kΩ

Differential

Outputs

V

OH

Output High Voltage

FOUT0, nFOUT0,

FOUT1, nFOUT1

V

cc

-

1.4 V

cc

-

1.0

V

OL

Output Low Voltage

V

cc

-

2.0 V

cc

-

1.7

V

P

-

P

Peak to Peak Output Voltage

1

Note 1: Single-ended measurement. See Figure 6, Output Rise and Fall Time, on pg. 9.

0.4 0.85

V

LVC MOS

Output

V

OH

Output High Voltage

LOL

2.4

V

CC

V

I

OH

= 1mA

V

OL

Output Low Voltage

GND 0.4

V

I

OL

= 1mA

Table 10: DC Characteristics

M2020/21 Datasheet Rev 1.1 9 of 10 Revised 20Jul2009

Integrated Circuit Systems, Inc.

●

Networking & Communications

●

www.icst.com

●

tel (508) 852-5400

M2020/21

VCSO B

ASED

C

LOCK

PLL

Product Data Sheet

Integrated

Circuit

Systems, Inc.

E

LECTRICAL

S

PECIFICATIONS

(

CONTINUED

)

P

ARAMETER

M

EASUREMENT

I

NFORMATION

Output Rise and Fall Time

Figure 6: Output Rise and Fall Time

Output Duty Cycle

Figure 7: Output Duty Cycle

AC Characteristics

Unless stated otherwise, V

CC

=

3.3

V +

5

%,T

A

=

0

o

C

to +

70

o

C (commercial), T

A

=

-40

o

C

to +

85

o

C (industrial), F

VCSO

= F

OUT

=

622-675

MHz,

LVPECL outputs terminated with

50

Ω

to V

CC

- 2V

Symbol Parameter Min Typ Max Unit Conditions

F

IN

Input Frequency

DIF_REF0, nDIF_REF0,

DIF_REF1, nDIF_REF1

10 700

MHz

F

OUT

Output Frequency

FOUT0, nFOUT

0,

FOUT1, nFOUT

1 15 700

MHz

APR

VCSO Absolute

Pull-Range

Commercial

±

120

±

200

ppm

Industrial

±

50

±

150

ppm

PLL Loop

Constants

1

Note 1: Parameters needed for PLL Simulator software; see Table 7, Example Values for Loop Filter External Components, on pg. 7.

K

VCO

VCO Gain

800

kHz/V

R

IN

Internal Loop Resistor

Wide Bandwidth

100

kΩ

Narrow Bandwidth

2100

kΩ

BW

VCSO

VCSO Bandwidth

700

kHz

Phase Noise

and Jitter

Φ

n Single Side Band

Phase Noise

@

622.08

MHz

1

kHz Offset -

73

dBc/Hz

Fin=19.44 or

38.88 MHz

Mfin=32 or 16,

M=1, R=1

10

kHz Offset -

103

dBc/Hz

100

kHz Offset -

126

dBc/Hz

J(t) Jitter (rms)

@

622.08

MHz

12

kHz to

20

MHz

0.25 0.5

ps

50

kHz to

80

MHz

0.25 0.5

ps

odc Output Duty Cycle

2

Note 2: See Parameter Measurement Information on pg. 9.

P = 4, 8, or 32

45 50 55

%

P = 1

40 50 60

%

t

R

Output Rise Time

2

for

FOUT0, nFOUT

0,

FOUT1, nFOUT

1

200 450 500

ps

20

%

to

80

%

t

F

Output Fall Time

2

for

FOUT0, nFOUT

0,

FOUT1, nFOUT

1

200 450 500

ps

20

%

to

80

%

Table 11: AC Characteristics

20%

80%

t

R

20%

t

F

80%

Clock Output

V

P

-

P

nFOUT

FOUT

t

PW

t

PERIOD

(Output Pulse Width)

t

PERIOD

t

PW

odc =

M2020-13-622.0800

M2020-13-622.0800

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