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NB4L6254MNR4G

P1-P3P4-P6P7-P9P10-P11
© Semiconductor Components Industries, LLC, 2009
March, 2009 − Rev. 3
1 Publication Order Number:
NB4L6254/D
NB4L6254
2.5V / 3.3V Differential
LVPECL 2x2 Clock Switch
and Low Skew Fanout
Buffer
Description
The NB4L6254 is a differential 2x2 clock switch and drives
precisely aligned clock signals through its LVPECL fanout buffers. It
employs a fully differential architecture with bipolar technology,
offers superior digital signal characteristics, has very low clock output
skew and supports clock frequencies from DC up to 3.0 GHz.
The NB4L6254 is designed for the most demanding, skew critical
differential clock distribution systems. Typical applications for the
NB4L6254 are clock distribution, switching and data loopback
systems of high−performance computer, networking and
telecommunication systems, as well as on−board clocking of OC−3,
OC−12 and OC−48 communication systems. In addition, the
NB4L6254 can be configured as a single 1:6 or dual 1:3 LVPECL
fanout buffer.
The NB4L6254 can be operated from a single 3.3 V or 2.5 V power
supply.
Features
• Maximum Clock Input Frequency, 3 GHz
• Maximum Input Data Rate, 3 Gb/s
• Differential LVPECL Inputs and Outputs
• Low Output Skew: 50 ps Maximum Output−to−Output Skew
• Synchronous Output Enable Eliminating Output Runt Pulse
Generation and Metastability
• Operating Range: Single 3.3 V or 2.5 V Supply
V
CC
= 2.375 V to 3.465 V
• LVCMOS Compatible Control Inputs
• Packaged in LQFP−32
• Fully Differential Architecture
• −40°C to 85°C Ambient Operating Temperature
• These are Pb−Free Devices*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
LQFP−32
FA SUFFIX
CASE 873A
MARKING DIAGRAMS*
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
NB4L
6254
AWLYYWWG
32
1
NB4L6254
AWLYYWWG
G
1
QFN32
MN SUFFIX
CASE 488AM
OEA
QA0
QA0
QA1
QA1
QA2
QA2
QB0
QB0
QB1
QB1
QB2
QB2
0
1
0
1
Bank A
Bank B
OEB
SEL0
SEL1
CLK1
CLK1
CLK0
CLK0
V
CC
V
CC
Figure 1. Functional Block Diagram
SYNC
NB4L6254
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2
GND
V
CC
OEA
CLK0
CLK0
V
CC
SEL0
GND
QB2 QB2QB1 QB1QB0 QB0
QA2
QA2
V
CC
V
CC
OEB
CLK1
QA1
V
CC
GND
V
CC
QA1V
CC
QA0QA0
GND
SEL1
CLK1
V
CC
Figure 2. 32−Lead LQFP Pinout (Top View)
NB4L6254
2526272829303132
1514131211109
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
Figure 3. 32−Lead QFN Pinout (Top View)
2526272829303132
1514131211109
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
GND
V
CC
OEA
CLK0
CLK0
V
CC
SEL0
GND
QB2 QB2QB1 QB1QB0 QB0
QA2 QA2
V
CC
V
CC
OEB
CLK1
QA1
V
CC
GND
V
CC
QA1V
CC
QA0QA0
GND
SEL1
CLK1
V
CC
NB4L6254
Exposed Pad
(EP)
NB4L6254
http://onsemi.com
3
Table 1. PIN DESCRIPTION
Pin Name I/O Description
CLK0, CLK0 LVPECL Input Differential reference clock signal input 0.
CLK1, CLK1 LVPECL Input Differential reference clock signal input 1.
OEAb, OEB LVCMOS Input Output Enable
SEL0, SEL1 LVCMOS Input Clock Switch Select
QA[0−2], QA[0−2]
QB[0−2], QB[0−2]
LVPECL Output
Differential LVPECL Clock Outputs, (banks A and B) Typically terminated with 50 W
resistor to V
CC
– 2.0 V.
GND Power Supply Negative Supply Voltage
V
CC
Power Supply Positive supply voltage. All V
CC
pins must be connected to the positive power supply
for correct DC and AC operation.
EP The exposed pad (EP) on the QFN−32 package bottom is thermally connected to the
die for improved heat transfer out of the package. THe exposed pad must be attached
to a heat−sinking conduit. The pad is electrically connected to GND.
Table 2. FUNCTION TABLE
Control Default 0 1
OEA 0 QA[0−2], QA[0−2] are active. Deassertion of
OEA can be asynchronous to the reference
clock without generation of output runt pulses
QA[0−2] = L, QA[0−2] = H (outputs disabled). Assertion of
OE can be asynchronous to the reference clock without
generation of output runt pulses
OEB 0 QB[0−2], QB[0−2] are active. Deassertion of
OEB can be asynchronous to the reference
clock without generation of output runt pulses
QB[0−2] = L, QB[0−2] = H (outputs disabled). Assertion of
OE can be asynchronous to the reference clock without
generation of output runt pulses
SEL0,
SEL1
00 Refer to Table 3 Refer to Table 3
Table 3. CLOCK SELECT CONTROL
SEL0 SEL1 CLK0 Routed To CLK1 Routed to Application Mode
0 0 QA[0:2] and QB[0:2] − 1:6 Fanout of CLK0
0 1 − QA[0:2] and QB[0:2] 1:6 Fanout of CLK1
1 0 QA[0:2] QB[0:2] Dual 1:3 Buffer
1 1 QB[0:2] QA[0:2] Dual 1:3 Buffer (Crossed)
P1-P3P4-P6P7-P9P10-P11

NB4L6254MNR4G

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Buy NB4L6254MNR4G
Manufacturer:
ON Semiconductor
Description:
Clock Drivers & Distribution LVPECL 2X2 SWITCH FANOUT
Lifecycle:
New from this manufacturer.
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