MARCH 8, 2017 3 7-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS
9DBU0741 DATASHEET
Pin Descriptions
PIN # PIN NAME
PIN
DESCRIPTION
1 vSADR_tri
LATCHE
D IN
Tri-level latch to select SMBus Address. It has an internal 120kohm pull down resistor.
See SMBus Address Selection Table.
2vOE6# IN
Active low input for enabling output 6. This pin has an internal 120kohm pull-down.
1 =disable outputs, 0 = enable outputs
3 DIF6 OUT Differential true clock output.
4 DIF6# OUT Differential complementary clock output.
5 VDDR1.5 PWR
1.5V power for differential input clock (receiver). This VDD should be treated as an
Analo
power rail and filtered appropriately.
6 CLK_IN IN True Input for differential reference clock.
7 CLK_IN# IN Complementary Input for differential reference clock.
8 GNDDIG GND Ground pin for digital circuitry.
9 SCLK_3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant.
10 SDATA_3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant.
11 VDDDIG1.5 PWR 1.5V di
ital power (dirty power)
12 VDDIO PWR Power supply for differential outputs
13 vOE0# IN
Active low input for enabling output 0. This pin has an internal 120kohm pull-down.
1 =disable outputs, 0 = enable outputs
14 DIF0 OUT Differential true clock output.
15 DIF0# OUT Differential complementary clock output.
16 VDD1.5 PWR Power supply, nominally 1.5V
17 VDDIO PWR Power supply for differential outputs
18 DIF1 OUT Differential true clock output.
19 DIF1# OUT Differential complementary clock output.
20 NC N/A No connection.
21 vOE1# IN
Active low input for enabling output 1. This pin has an internal 120kohm pull-down.
1 =disable outputs, 0 = enable outputs
22 DIF2 OUT Differential true clock output.
23 DIF2# OUT Differential complementary clock output.
24 vOE2# IN
Active low input for enabling output 2. This pin has an internal 120kohm pull-down.
1 =disable outputs, 0 = enable outputs
25 VDDO1.5 PWR Power supply for outputs, nominally 1.5V.
26 VDDIO PWR Power supply for differential outputs
27 DIF3 OUT Differential true clock output.
28 DIF3# OUT Differential complementary clock output.
29 vOE3# IN
Active low input for enabling output 3. This pin has an internal 120kohm pull-down.
1 =disable outputs, 0 = enable outputs
30 NC N/A No connection.
31 VDD1.5 PWR Power supply, nominally 1.5V
32 VDDIO PWR Power supply for differential outputs
33 DIF4 OUT Differential true clock output.
34 DIF4# OUT Differential complementary clock output.
35 vOE4# IN
Active low input for enabling output 4. This pin has an internal 120kohm pull-down.
1 =disable outputs, 0 = enable outputs
36 DIF5 OUT Differential true clock output.
37 DIF5# OUT Differential complementary clock output.
38 vOE5# IN
Active low input for enabling output 5. This pin has an internal 120kohm pull-down.
1 =disable outputs, 0 = enable outputs
39 VDDIO PWR Power supply for differential outputs
40 ^CKPWRGD_PD# IN
Input notifies device to sample latched inputs and start up on first high assertion. Low
enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin
has internal 120kohm pull-up resistor.
41 EPAD GND Connect paddle to ground.
