9DBU0741AKILF Datasheet 9DBU0741AKLF, 9DBU0741AKILF | P10-P12

7-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 10 MARCH 8, 2017

9DBU0741 DATASHEET

General SMBus Serial Interface Information

How to Write

• Controller (host) sends a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) sends the byte count = X

• IDT clock will acknowledge

• Controller (host) starts sending Byte N through Byte

N+X-1

• IDT clock will acknowledge each byte one at a time

• Controller (host) sends a stop bit

Note: SMBus Address is Latched on SADR pin.

How to Read

• Controller (host) will send a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) will send a separate start bit

• Controller (host) sends the read address

• IDT clock will acknowledge

• IDT clock will send the data byte count = X

• IDT clock sends Byte N+X-1

• IDT clock sends Byte 0 through Byte X (if X

(H)

was

written to Byte 8)

• Controller (host) will need to acknowledge each byte

• Controller (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

Index Block Write Operation

Controller (Host) IDT (Slave/Receiver)

TstarT bit

Slave Address

WR WRite

ACK

Beginning Byte = N

ACK

Data Byte Count = X

ACK

Beginning Byte N

X Byte

ACK

O O

Byte N + X - 1

ACK

PstoP bit

Index Block Read Operation

Controller (Host) IDT (Slave/Receiver)

TstarT bit

Slave Address

WR WRite

ACK

Beginning Byte = N

ACK

RT Repeat starT

Slave Address

RD ReaD

ACK

Data Byte Count=X

ACK

X Byte

Beginning Byte N

ACK

O O

Byte N + X - 1

N Not acknowledge

PstoP bit

MARCH 8, 2017 11 7-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS

9DBU0741 DATASHEET

SMBus Table: Output Enable Register

Byte 0 Name Control Function Type 0 1 Default

Bit 7

DIF OE5 Output Enable RW Low/Low Enabled 1

Bit 6

DIF OE4 Output Enable RW Low/Low Enabled 1

Bit 5

Bit 4

DIF OE3 Output Enable RW Low/Low Enabled 1

Bit 3

DIF OE2 Output Enable RW Low/Low Enabled 1

Bit 2

DIF OE1 Output Enable RW Low/Low Enabled 1

Bit 1

Bit 0

DIF OE0 Output Enable RW Low/Low Enabled 1

1. A low on these bits will override the OE# pin and force the differential output Low/Low

SMBus Table: PLL Operating Mode and Output Amplitude Control Register

Byte 1 Name Control Function Type 0 1 Default

Bit 7

Bit 6

Bit 5

DIF OE6 Output Enable RW Low/Low Enabled 1

Bit 4

Bit 3

Bit 2

Bit 1

AMPLITUDE 1 RW 00 = 0.55V 01= 0.65V 1

Bit 0

AMPLITUDE 0 RW 10 = 0.7V 11 = 0.8V 0

1. A low on the DIF OE bit will override the OE# pin and force the differential output Low/Low

SMBus Table: DIF Slew Rate Control Register

Byte 2 Name Control Function Type 0 1 Default

Bit 7

SLEWRATESEL DIF5 Adjust Slew Rate of DIF5 RW Slow Setting Fast Setting 1

Bit 6

SLEWRATESEL DIF4 Adjust Slew Rate of DIF4 RW Slow Setting Fast Setting 1

Bit 5

Bit 4

SLEWRATESEL DIF3 Adjust Slew Rate of DIF3 RW Slow Setting Fast Setting 1

Bit 3

SLEWRATESEL DIF2 Adjust Slew Rate of DIF2 RW Slow Setting Fast Setting 1

Bit 2

SLEWRATESEL DIF1 Adjust Slew Rate of DIF1 RW Slow Setting Fast Setting 1

Bit 1

Bit 0

SLEWRATESEL DIF0 Adjust Slew Rate of DIF0 RW Slow Setting Fast Setting 1

Note: See "DIF 0.7V Low-Power HCSL Outputs" table for slew rates.

SMBus Table: DIF Slew Rate Control Register

Byte 3 Name Control Function Type 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SLEWRATESEL DIF6 Adjust Slew Rate of DIF6 RW Slow Setting Fast Setting 1

Note: See "DIF 0.7V Low-Power HCSL Outputs" table for slew rates.

Byte 4 is Reserved and reads back 'hFF

Reserved

Controls Output Amplitude

Reserved

7-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 12 MARCH 8, 2017

9DBU0741 DATASHEET

SMBus Table: Revision and Vendor ID Register

Byte 5 Name Control Function Type 0 1 Default

Bit 7

RID3

Bit 6

RID2

Bit 5

RID1

Bit 4

RID0

Bit 3

VID3

Bit 2

VID2

Bit 1

VID1

Bit 0

VID0

SMBus Table: Device Type/Device ID

Byte 6 Name Control Function Type 0 1 Default

Bit 7

Device Type1

Bit 6

Device Type0

Bit 5

Device ID5

Bit 4

Device ID4

Bit 3

Device ID3

Bit 2

Device ID2

Bit 1

Device ID1

Bit 0

Device ID0

SMBus Table: Byte Count Register

Byte 7 Name Control Function Type 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

BC4 RW 0

Bit 3

BC3 RW 1

Bit 2

BC2 RW 0

Bit 1

BC1 RW 0

Bit 0

BC0 RW 0

Reserved

Byte Count Programming

Writing to this register will configure how

many bytes will be read back, default is

= 8 bytes.

VENDOR ID 0001 = IDT

Device Type

00 = FGx, 01 = DBx,

10 = DMx, 11= DBx w/oPLL

Device ID 000111 binary or 07 hex

Revision ID A rev = 0000

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

9DBU0741AKILF

Mfr. #:

Buy 9DBU0741AKILF

Manufacturer:

IDT

Description:

Clock Buffer 2 O/P 1.5V PCIE 45mW GEN1-2-3 Ind 100ohm

Lifecycle:

New from this manufacturer.

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9DBU0741AKILF

9DBU0741AKILF

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