7-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 4 MARCH 8, 2017
9DBU0741 DATASHEET
Test Loads
Driving LVDS
Rs
Rs
Low-Power HCSL Differential Output Test Load
2pF 2pF
5 inches
Zo=100
Note: The device can drive transmission line lengths greater
than those allowed by the PCIe SIG
Rs
Device
Rs
Zo
Driving LVDS
Cc
Cc
R7a R7b
R8a
R8b
LVDS Clock
input
3.3V
Driving LVDS inputs
Receiver has
termination
Receiver does not
have termination
R7a, R7b 10K ohm 140 ohm
R8a, R8b 5.6K ohm 75 ohm
Cc 0.1µF 0.1µF
Vcm 1.2 volts 1.2 volts
Component
Value
Note
MARCH 8, 2017 5 7-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS
9DBU0741 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBU0741. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
Electrical Characteristics–Clock Input Parameters
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
Supply Voltage VDDx Applies to VDD, VDDA and VDDIO -0.5 2 V 1,2
Input Voltage V
IN
-0.5 V
DD
+0.5 V 1,
Input High Voltage, SMBus V
IHSMB
SMBus clock and data pins 3.3 V 1
Storage Temperature Ts -65 150 °C 1
Junction Temperature Tj 125 °C 1
Input ESD protection
ESD prot Human Body Model 2000 V 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 2.0V.
TA = T
AMB,
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input Common Mode
Voltage - DIF_IN
V
COM
Common Mode Input Voltage 200 725 mV 1
Input Swing - DIF_IN V
SWING
Differential value 300 1450 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
=
GND -5 5 µA
Input Duty Cycle d
tin
Measurement from differential waveform 45 50 55 % 1
Input Jitter - Cycle to Cycle J
DIFIn
Differential Measurement 0 150 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through +/-75mV window centered around differential zero.
7-OUTPUT 1.5V PCIE GEN1-2-3 FANOUT BUFFER WITH ZO=100OHMS 6 MARCH 8, 2017
9DBU0741 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T
AMB
; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Supply Voltage VDDx Supply voltage for core and analog 1.425 1.5 1.575 V
Output Supply Voltage VDDIO Low Voltage Supply LP-HCSL Outputs 0.95 1.05-1.5 1.575 V
Commercial range 0 25 70 °C
1
Industrial range -40 25 85 °C 1
Input High Voltage V
IH
Single-ended inputs, except SMBus 0.75 V
DD
V
DD
+ 0.3 V
Input Mid Voltage V
IM
Single-ended tri-level inputs ('_tri' suffix) 0.4 V
DD
0.6 V
DD
V
Input Low Voltage V
IL
Single-ended inputs, except SMBus -0.3 0.25 V
DD
V
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 µA
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 µA
Input Frequency F
in
1 167 MHz 2
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
INDIF_I N
DIF_IN differential clock inputs 1.5 2.7 pF 1,5
C
OU
T
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1ms1,2
Input SS Modulation
Frequency PCIe
f
MODINPCI e
Allowable Frequency for PCIe Applications
(Triangular Modulation)
30 33 kHz
Input SS Modulation
Frequency non-PCIe
f
MODIN
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
066kHz
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1 3 clocks 1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 µs 1,3
Tfall t
F
Fall time of single-ended control inputs 5 ns 2
Trise t
R
Rise time of single-ended control inputs 5 ns 2
SMBus Input Low Voltage V
ILSMB
0.6 V
SMBus Input High Voltage V
IHSMB
V
DDSMB
= 3.3V, see note 4 for V
DDSMB
< 3.3V 2.1 3.3 V 4
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V
SMBus Sink Current I
PULLUP
@ V
OL
4mA
Nominal Bus Voltage V
DDSMB
Bus Voltage 1.425 3.3 V
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating frequency 400 kHz 6
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until outputs are > 200 mV.
4
For V
DDSMB
< 3.3V, V
IHSMB
>= 0.8xV
DDSMB.
5
DIF_IN input.
6
The differential input clock must be running for the SMBus to be active.
Input Current
Capacitance
Ambient Operating
Temperature
T
AMB

9DBU0741AKLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 2 O/P 1.5V PCIE 45mW GEN1-2-3 Com 100ohm
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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