P89LPC9311FDH,129 Datasheet P89LPC9311FDH,129, P89LPC931FDH,112, P89LPC930FDH,129 | P37-P39

Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Product data Rev. 05 — 15 December 2004 37 of 55

9397 750 14472

8.22 Watchdog timer

The watchdog timer causes a system reset when it underﬂows as a result of a failure

to feed the timer prior to the timer reaching its terminal count. It consists of a

programmable 12-bit prescaler, and an 8-bit down counter. The down counter is

decremented by a tap taken from the prescaler. The clock source for the prescaler is

either the PCLK or the nominal 400 kHz Watchdog oscillator. The watchdog timer can

only be reset by a power-on reset. When the Watchdog feature is disabled, it can be

used as an interval timer and may generate an interrupt. Figure 14 shows the

watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte

sequence. If PCLK is selected as the Watchdog clock and the CPU is powered-down,

the watchdog is disabled. The watchdog timer has a time-out period that ranges from

a few µs to a few seconds. Please refer to the

P89LPC930/931 User’s Manual

for

more details.

8.23 Additional features

8.23.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor

completely, as if an external reset or Watchdog reset had occurred. Care should be

taken when writing to AUXR1 to avoid accidental software resets.

8.23.2 Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the

address used with certain instructions. The DPS bit in the AUXR1 register selects

one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic ‘0’ so

that the DPS bit may be toggled (thereby switching Data Pointers) simply by

incrementing the AUXR1 register, without the possibility of inadvertently altering other

bits in the register.

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a

feed sequence.

Fig 14. Watchdog timer in Watchdog mode (WDTE = ‘1’).

PRE2 PRE1 PRE0 – – WDRUN WDTOF WDCLK

WDCON (A7H)

CONTROL REGISTER

PRESCALER

002aaa423

SHADOW

FOR WDCON

8-BIT DOWN

COUNTER

WDL (C1H)

Watchdog

oscillator

PCLK

÷32

MOV WFEED1, #0A5H

MOV WFEED2, #05AH

RESET

see note (1)

Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Product data Rev. 05 — 15 December 2004 38 of 55

9397 750 14472

8.24 Flash program memory

8.24.1 General description

The P89LPC930/931 Flash memory provides in-circuit electrical erasure and

programming. The Flash can be read, erased, or written as bytes. The Sector and

Page Erase functions can erase any Flash sector (1 kB) or page (64 bytes). The Chip

Erase operation will erase the entire program memory. In-System Programming and

standard parallel programming are both available. On-chip erase and write timing

generation contribute to a user-friendly programming interface. The P89LPC930/931

Flash reliably stores memory contents even after more than 100,000 erase and

program cycles. The cell is designed to optimize the erase and programming

mechanisms. The P89LPC930/931 uses V

as the supply voltage to perform the

Program/Erase algorithms.

8.24.2 Features

• Byte-erase allowing code memory to be used for data storage.

• Internal ﬁxed boot ROM, containing low-level In-Application Programming (IAP)

routines.

• User programs can call these routines to perform In-Application Programming

(IAP).

• Default loader providing In-System Programming via the serial port, located in

upper end of user program memory.

• Boot vector allows user-provided Flash loader code to reside anywhere in the

Flash memory space, providing ﬂexibility to the user.

• Programming and erase over the full operating voltage range.

• Programming/Erase using ISP/IAP.

• Any ﬂash program/erase operation in 2 ms.

• Parallel programming with industry-standard commercial programmers.

• Programmable security for the code in the Flash for each sector.

• More than 100,000 typical erase/program cycles for each byte.

• 10 year minimum data retention.

8.24.3 Using Flash as data storage

The Flash code memory array of this device supports individual byte erasing and

programming. Any byte in the code memory array may be read using the MOVC

instruction, provided that the sector containing the byte has not been secured (a

MOVC instruction is not allowed to read code memory contents of a secured sector).

Thus any byte in a non-secured sector may be used for non-volatile data storage.

8.24.4 ISP and IAP capabilities of the P89LPC930/931

Flash organization: The P89LPC930/931 program memory consists of eight 1 KB

sectors. Each sector can be further divided into 64-byte pages. In addition to sector

erase and page erase, a 64-byte page register is included which allows from 1 to 64

bytes of a given page to be programmed at the same time, substantially reducing

overall programming time. An In-Application Programming (IAP) interface is provided

to allow the end user’s application to erase and reprogram the user code memory. In

Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Product data Rev. 05 — 15 December 2004 39 of 55

9397 750 14472

addition, erasing and reprogramming of user-programmable bytes including UCFG1,

the Boot Status Bit, and the Boot Vector is supported. As shipped from the factory,

the upper 512 bytes of user code space contains a serial In-System Programming

(ISP) routine allowing for the device to be programmed in circuit through the serial

port.

Flash programming and erasing: There are three methods of erasing or

programming of the Flash memory that may be used. First, the Flash may be

programmed or erased in the end-user application by calling low-level routines

through a common entry point. Second, the on-chip ISP boot loader may be invoked.

This ISP boot loader will, in turn, call low-level routines through the same common

entry point that can be used by the end-user application. Third, the Flash may be

programmed or erased using the parallel method by using a commercially available

EPROM programmer which supports this device. This device does not provide for

direct veriﬁcation of code memory contents. Instead this device provides a 32-bit

CRC result on either a sector or the entire 8 kbytes of user code space.

Boot ROM: When the microcontroller programs its own Flash memory, all of the low

level details are handled by code that is contained in a Boot ROM that is separate

from the Flash memory. A user program simply calls the common entry point in the

Boot ROM with appropriate parameters to accomplish the desired operation. The

Boot ROM include operations such as erase sector, erase page, program page, CRC,

program security bit, etc. The Boot ROM occupies the program memory space at the

top of the address space from FF00 to FEFF hex, thereby not conﬂicting with the user

program memory space.

Power-on reset code execution: The P89LPC930/931 contains two special Flash

elements: the Boot Vector and the Boot Status Bit. Following reset, the

P89LPC930/931 examines the contents of the Boot Status Bit. If the Boot Status Bit

is set to zero, power-up execution starts at location 0000H, which is the normal start

address of the user’s application code. When the Boot Status Bit is set to a value

other than zero, the contents of the Boot Vector is used as the high byte of the

execution address and the low byte is set to 00H. The factory default setting is 01EH

(0EH for the LPC930), corresponds to the address 1E00H (0E00h for the LPC930) for

the default ISP boot loader. This boot loader is pre-programmed at the factory into

this address space and can be erased by the user. Users who wish to use this

loader should take cautions to avoid erasing the 1 kbyte sector from 1C00H to

1FFFH (0C00H to 0FFFH for the LPC930). Instead, the page erase function can

be used to erase the eight (four for the LPC930) 64-byte pages located from

1C00H to 1DFFH (0C00H to 0DFFH for the LPC930). A custom boot loader can be

written with the Boot Vector set to the custom boot loader, if desired.

Hardware activation of the boot loader: The boot loader can also be executed by

forcing the device into ISP mode during a power-on sequence (see the

P89LPC930/931 User’s Manual

for speciﬁc information). This has the same effect as

having a non-zero status byte. This allows an application to be built that will normally

execute user code but can be manually forced into ISP operation. If the factory default

setting for the Boot Vector (1EH for the lPC931, 0EH for the LPC930) is changed, it

will no longer point to the factory pre-programmed ISP boot loader code. If this

happens, the only way it is possible to change the contents of the Boot Vector is

through the parallel programming method, provided that the end user application

does not contain a customized loader that provides for erasing and reprogramming of

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IC MCU 8BIT 8KB FLASH 28TSSOP

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