Philips Semiconductors
P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
Product data Rev. 05 — 15 December 2004 46 of 55
9397 750 14472
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table 9: AC characteristics
V
DD
= 3.0 V to 3.6 V, unless otherwise specified.
T
amb
=
−
40
°
Cto+85
°
C for industrial, unless otherwise specified.
[1]
Symbol Parameter Conditions Variable clock f
osc
=18MHz Unit
Min Max Min Max
f
RCOSC
internal RC oscillator frequency 7.189 7.557 7.189 7.557 MHz
f
WDOSC
internal Watchdog oscillator
frequency
320 520 320 520 kHz
f
osc
oscillator frequency
[2]
0 18 - - MHz
t
CLCL
clock cycle see Figure 20 55- --ns
f
CLKP
CLKLP active frequency 0 8 - - MHz
Glitch filter
glitch rejection, P1.5/
RST pin - 50 - 50 ns
signal acceptance, P1.5/
RST pin 125 - 125 - ns
glitch rejection, any pin except
P1.5/
RST
- 15 - 15 ns
signal acceptance, any pin except
P1.5/
RST
50 - 50 - ns
External clock
t
CHCX
HIGH time see Figure 20 22 t
CLCL
− t
CLCX
22 - ns
t
CLCX
LOW time see Figure 20 22 t
CLCL
− t
CHCX
22 - ns
t
CLCH
rise time see Figure 20 -5 -5ns
t
CHCL
fall time see Figure 20 -5 -5ns
Shift register (UART mode 0)
t
XLXL
serial port clock cycle time 16 t
CLCL
- 888 - ns
t
QVXH
output data set-up to clock rising
edge
13 t
CLCL
- 722 - ns
t
XHQX
output data hold after clock rising
edge
-t
CLCL
+ 20 - 75 ns
t
XHDX
input data hold after clock rising
edge
-0 -0ns
t
DVXH
input data valid to clock rising edge 150 - 150 - ns
SPI interface
f
SPI
Operating frequency
3.0 MHz (Slave) 0
CCLK
⁄
6
0 3 MHz
4.5 MHz (Master) -
CCLK
⁄
4
- 4.5 MHz
t
SPICYC
Cycle time see Figures
15, 16, 17, 18
3.0 MHz (Slave)
6
⁄
CCLK
- 333 - ns
4.5 MHz (Master)
4
⁄
CCLK
- 222 - ns
