MAX9123
Quad LVDS Line Driver with
Flow-Through Pinout
_______________________________________________________________________________________ 7
Eliminate reflections and ensure that noise couples as
common mode by running the differential trace pairs
close together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
Maintain the distance between the differential traces to
avoid discontinuities in differential impedance. Avoid
90° turns and minimize the number of vias to further
prevent impedance discontinuities.
Cables and Connectors
Transmission media should have a nominal differential
impedance of 100. To minimize impedance disconti-
nuities, use cables and connectors that have matched
differential impedance.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by the LVDS receiver.
Board Layout
For LVDS applications, a four-layer PC board that pro-
vides separate power, ground, LVDS signals, and input
signals is recommended. Isolate the LVTTL/LVCMOS
and LVDS signals from each other to prevent coupling.
Chip Information
TRANSISTOR COUNT: 1246
PROCESS: CMOS
V
OS
V
CC
GND
IN_
R
L
/2
R
L
/2
V
OS
V
OD
OUT_-
OUT_+
R
L
C
L
OUT_ +
OUT_ -
C
L
50
IN_
GENERATOR
Figure 1. Driver V
OD
and V
OS
Test Circuit
Figure 2. Driver Propagation Delay and Transition Time Test
Circuit
0
V
OH
V
OL
IN_
OUT_
-
OUT_+
V
DIFF
3V
t
PHLD
1.5V
0
t
THL
20%
0
80%
80%
0
t
TLH
20%
0 DIFFERENTIAL
t
PLHD
1.5V
V
DIFF
= (V
OUT_
+) - (V
OUT_
-)
Figure 3. Driver Propagation Delay and Transition Time Waveforms
MAX9123
Quad LVDS Line Driver with
Flow-Through Pinout
8 _______________________________________________________________________________________
1.5V
EN WHEN EN = 0 OR OPEN
EN WHEN EN = V
CC
OUT_+ WHEN IN_ = 0
OUT_- WHEN IN_ = V
CC
OUT_+ WHEN IN_ = V
CC
OUT_- WHEN IN_ = 0
1.5V
1.5V
t
PLZ
t
PHZ
t
PZL
t
PZH
1.5V
3V
0
3V
1.2V
V
OL
V
OH
1.2V
0
50%50%
50%50%
Figure 5. Driver High-Impedance Delay Waveform
EN
GND
EN
IN_
OUT_-
OUT_+
1/4 MAX9123
GENERATOR
+1.2V
50
C
L
R
L/2
R
L/2
V
CC
C
L
Figure 4. Driver High-Impedance Delay Test Circuit
OUT1+
OUT1-
OUT2+
OUT2-
OUT3+
OUT3-
OUT4+
OUT4-
EN
EN
IN1
IN2
IN3
IN4
Functional Diagram
MAX9123
Quad LVDS Line Driver with
Flow-Through Pinout
_______________________________________________________________________________________ 9
Package Information
TSSOP,NO PADS.EPS

MAX9123EUE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
LVDS Interface IC Quad LVDS Line Driver
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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