DS016 (v2.6) March 31, 2006 www.xilinx.com 1
Product Specification
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All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
• Low power 3.3V 128 macrocell CPLD
• 5.5 ns pin-to-pin logic delays
• System frequencies up to 175 MHz
• 128 macrocells with 3,000 usable gates
• Available in small footprint packages
- 144-pin TQFP (108 user I/O pins)
- 144-ball CS BGA (108 user I/O)
- 100-pin VQFP (84 user I/O)
• Optimized for 3.3V systems
- Ultra low power operation
- Typical Standby Current of 17 μA at 25°
C
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM
process
- Fast Zero Power™ (FZP) CMOS design
technology
- 3.3V PCI electrical specification compatible outputs
(no internal clamp diode on any input or I/O)
• Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 available clocks per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
• Fast ISP programming times
• Port Enable pin for additional I/O
• 2.7V to 3.6V supply voltage at industrial temperature
range
• Programmable slew rate control per output
• Security bit prevents unauthorized access
• Refer to XPLA3 family data sheet (DS012
) for
architecture description
Description
The CoolRunner™ XPLA3 XCR3128XL device is a 3.3V
128 macrocell CPLD targeted at power sensitive designs
that require leading edge programmable logic solutions. A
total of eight function blocks provide 3,000 usable gates.
Pin-to-pin propagation delays are as fast as 5.5 ns with a
maximum system frequency of 175 MHz.
TotalCMOS Design Technique for Fast
Zero Power
CoolRunner XPLA3 CPLDs offer a TotalCMOS™ solution,
both in process technology and design technique. Xilinx
employs a cascade of CMOS gates to implement its sum of
products instead of the traditional sense amp approach.
This CMOS gate implementation allows Xilinx CPLDs to
offer devices that are both high performance and low power,
breaking the paradigm that to have low power, you must
have low performance. Refer to Figure 1 or Figure 2 and
Table 1or Ta ble 2 showing the I
CC
vs. Frequency of the
XCR3128XL TotalCMOS CPLD (data taken with eight
resetable up/down, 16-bit counters at 3.3V, 25°C).
0
XCR3128XL 128 Macrocell CPLD
DS016 (v2.6) March 31, 2006
014
Product Specification
R
Figure 1: Typical I
CC
vs. Frequency at V
CC
= 3.3V, 25°C
Frequency (MHz)
DS016_01_120902
Typical I
CC
(mA)
0
0
10
20
30
50
70
80
40
60
120 140 16010080604020
Table 1: Typical I
CC
vs. Frequency at V
CC
= 3.3V, 25°C
Frequency (MHz) 0 1 5 10 20 40 60 80 100 120 140 160
Typical I
CC
(mA) 0.017 0.5 2.48 4.97 9.89 19.7 29.5 39.1 48.7 58.0 67.3 76.8
