XCR3128XL 128 Macrocell CPLD
10 www.xilinx.com DS016 (v2.6) March 31, 2006
Product Specification
R
Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm
. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Additional Information
CoolRunner XPLA3 Data Sheets and Application Notes
Device Packages
Device Package User Guide
Revision History
The following table shows the revision history for this document.
XCR3128XL-10VQ100I 10 ns VQ100 100 Very Thin Quad Flat Package (VQFP) I
XCR3128XL-10VQG100I 10 ns VQG100 100 Very Thin Quad Flat Package (VQFP); Pb-Free I
XCR3128XL-10CS144I 10 ns CS144 144 Chip Scale Package (CSP) I
XCR3128XL-10CSG144I 10 ns CSG144 144 Chip Scale Package (CSP); Pb-Free I
XCR3128XL-10TQ144I 10 ns TQ144 144 Thin Quad Flat Pack (TQFP) I
XCR3128XL-10TQG144I 10 ns TQG144 144 Thin Quad Flat Pack (TQFP); Pb-Free I
Notes:
1. C = Commercial: T
A
= 0° to +70°C; I = Industrial: T
A
= –40° to +85°C
Device Ordering and
Part Marking Number
Speed
(pin-to-pin
delay)
Pkg.
Symbol
No. of
Pins Package Type
Operating
Range
(1)
Date Version Revision
04/07/00 1.0 Initial Xilinx release.
05/03/00 1.1 Minor updates and added Boundary Scan to pinout table.
11/20/00 1.2 Updated pinout tables; corrected note in Table 4 to read: "port enable pin is brought High".
12/08/00 1.3 Updated pinout tables.
01/17/01 1.4 Removed Timing Model.
04/11/01 1.5 Added Typical I/V curve, Figure 2; added Table 2: Total User I/O; changed V
OH
spec.
04/19/01 1.6 Updated Typical I/V curve, Figure 2: added voltage levels.
08/10/01 1.7 Moved Figure 1 and Table 1 to first page. Changed VQ144 to VQ100 in Ta bl e 2.
01/08/02 1.8 Updated T
SUF
and T
FIN
spec to match software timing. Added single p-term setup time (T
SU1
) to
AC Table, renamed T
SU
to T
SU2
for setup time through the OR array. Added T
INIT
spec. Updated
T
CONFIG
spec. Updated T
HI
spec to correct a typo. Updated AC Load Circuit diagram to more
closely resemble true test conditions, added note for T
POD
delay measurement.
01/27/03 1.9 Updated product availability and AC/DC parameters for -6 Commercial and -7 Industrial devices.
Updated T
PCO
(added T
PTCK
), T
CONFIG
, T
INIT
, T
F
. Updated I
CC
vs. Frequency Curve for -6 device;
updated system frequency to 175 MHz; removed Advance Information from -6 device; updated
Derating Curve for -6 device. Updated Ordering Information format.
