ULTRA LOW CURRENT CONSUMPTION, HIGH RIPPLE REJECTION AND LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.3.0_00
S-1167 Series
Seiko Instruments Inc.
11
Technical Terms
1. Low Dropout Voltage Regulator
The low dropout voltage regulator is a voltage regulator whose dropout voltage is low due to its built-in low on-
resistance transistor.
2. Low Equivalent Series Resistance
A capacitor whose equivalent series resistance (R
ESR
) is low. The S-1167 Series enables use of a low equivalent
series resistance capacitor, such as a ceramic capacitor, for the output-side capacitor (C
L
). A capacitor whose R
ESR
is 1.0 Ω or less can be used.
3. Output Voltage (V
OUT
)
The accuracy of the output voltage is ensured at ±1.0% under the specified conditions of fixed input voltage
*1
, fixed
output current, and fixed temperature.
*1. Differs depending on the product.
Caution If the above conditions change, the output voltage value may vary and exceed the accuracy range
of the output voltage. Refer to the “Electrical Characteristics” and “Typical Characteristics” for
details.
4. Line Regulation
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
•
OUTIN
OUT1
VΔV
ΔV
Indicates the dependency of the output voltage on the input voltage. That is, the values show how much the output
voltage changes due to a change in the input voltage with the output current remaining unchanged.
5. Load Regulation (ΔV
OUT2
)
Indicates the dependency of the output voltage on the output current. That is, the values show how much the output
voltage changes due to a change in the output current with the input voltage remaining unchanged.
6. Dropout Voltage (V
drop
)
Indicates the difference between the input voltage (V
IN1
), which is the input voltage (V
IN
) at the point where the output
voltage has fallen to 98% of the output voltage value (V
OUT3
) after V
IN
was gradually decreased from V
IN
= V
OUT(S)
+
1.0 V, and the output voltage at that point (V
OUT3
× 0.98).
V
drop
= V
IN1
− (V
OUT3
× 0.98)
