11
AT25080A/160A/320A/640A
3347G–SEEPR–7/04
READ SEQUENCE (READ): Reading the AT25080A/160A/320A/640A via the SO (Serial Out-
put) pin requires the following sequence. After the CS
line is pulled low to select a device, the
READ op-code is transmitted via the SI line followed by the byte address to be read (A15 - A0,
Refer to Table 6). Upon completion, any data on the SI line will be ignored. The data (D7 - D0)
at the specified address is then shifted out onto the SO line. If only one byte is to be read, the
CS
line should be driven high after the data comes out. The READ sequence can be contin-
ued since the byte address is automatically incremented and data will continue to be shifted
out. When the highest address is reached, the address counter will roll over to the lowest
address allowing the entire memory to be read in one continuous READ cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25080A/160A/320A/640A, two sep-
arate instructions must be executed. First, the device must be write enabled via the Write
Enable (WREN) Instruction. Then a Write (WRITE) Instruction may be executed. Also, the
address of the memory location(s) to be programmed must be outside the protected address
field location selected by the Block Write Protection Level. During an internal write cycle, all
commands will be ignored except the RDSR instruction.
A Write Instruction requires the following sequence. After the CS
line is pulled low to select the
device, the WRITE op-code is transmitted via the SI line followed by the byte address
(A15 - A0) and the data (D7 - D0) to be programmed (Refer to Table 6). Programming will start
after the CS
pin is brought high. (The LOW-to-High transition of the CS pin must occur during
the SCK low-time immediately after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device can be determined by initiating a READ STATUS
REGISTER (RDSR) Instruction. If Bit 0 = 1, the WRITE cycle is still in progress. If Bit 0 = 0, the
WRITE cycle has ended. Only the READ STATUS REGISTER instruction is enabled during
the WRITE programming cycle.
The AT25080A/160A/320A/640A is capable of a 32-byte PAGE WRITE operation. After each
byte of data is received, the five low order address bits are internally incremented by one; the
high order bits of the address will remain constant. If more than 32 bytes of data are transmit-
ted, the address counter will roll over and the previously written data will be overwritten. The
AT25080A/160A/320A/640A is automatically returned to the write disable state at the comple-
tion of a WRITE cycle.
NOTE: If the device is not Write enabled (WREN), the device will ignore the Write instruction
and will return to the standby state, when CS
is brought high. A new CS falling edge is
required to re-initiate the serial communication.
Table 6. Address Key
Address AT25080A AT25160A AT25320A AT25640A
A
N
A
9
- A
0
A
10
- A
0
A
11
- A
0
A
12
- A
0
Don't Care Bits A
15
- A
10
A
15
- A
11
A
15
- A
12
A
15
- A
13
