AT25080A-10PI-1.8 Datasheet AT25080A-10PI-2.7, AT25080AN-10SI-2.7, AT25160AN-10SI-2.7 | P7-P9

AT25080A/160A/320A/640A

3347G–SEEPR–7/04

Serial Interface

Description

MASTER: The device that generates the serial clock.

SLAVE: Because the Serial Clock pin (SCK) is always an input, the

AT25080A/160A/320A/640A always operates as a slave.

TRANSMITTER/RECEIVER: The AT25080A/160A/320A/640A has separate pins designated

for data transmission (SO) and reception (SI).

MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.

SERIAL OP-CODE: After the device is selected with CS

going low, the first byte will be

received. This byte contains the op-code that defines the operations to be performed.

INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the

AT25080A/160A/320A/640A, and the serial output pin (SO) will remain in a high impedance

state until the falling edge of CS

is detected again. This will reinitialize the serial

communication.

CHIP SELECT: The AT25080A/160A/320A/640A is selected when the CS

pin is low. When

the device is not selected, data will not be accepted via the SI pin, and the serial output pin

(SO) will remain in a high impedance state.

HOLD: The HOLD

pin is used in conjunction with the CS pin to select the

AT25080A/160A/320A/640A. When the device is selected and a serial sequence is underway,

HOLD

can be used to pause the serial communication with the master device without resetting

the serial sequence. To pause, the HOLD

pin must be brought low while the SCK pin is low.

To resume serial communication, the HOLD

pin is brought high while the SCK pin is low (SCK

may still toggle during HOLD

). Inputs to the SI pin will be ignored while the SO pin is in the

high impedance state.

WRITE PROTECT: The write protect pin (WP

) will allow normal read/write operations when

held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the sta-

tus register are inhibited. WP

going low while CS is still low will interrupt a write to the status

going low will have no effect

on any write operation to the status register. The WP

pin function is blocked when the WPEN

bit in the status register is “0”. This will allow the user to install the

AT25080A/160A/320A/640A in a system with the WP

pin tied to ground and still be able to

write to the status register. All WP

pin functions are enabled when the WPEN bit is set to “1”.

AT25080A/160A/320A/640A

3347G–SEEPR–7/04

SPI Serial Interface

AT25080A/160A/320A/640A

3347G–SEEPR–7/04

Functional

Description

The AT25080A/160A/320A/640A is designed to interface directly with the synchronous serial

peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers.

The AT25080A/160A/320A/640A utilizes an 8-bit instruction register. The list of instructions

and their operation codes are contained in Table 1. All instructions, addresses, and data are

transferred with the MSB first and start with a high-to-low CS transition.

WRITE ENABLE (WREN): The device will power-up in the write disable state when V

applied. All programming instructions must therefore be preceded by a Write Enable

instruction.

WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable

instruction disables all programming modes. The WRDI instruction is independent of the sta-

tus of the WP

pin.

READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to

the status register. The READY/BUSY and Write Enable status of the device can be deter-

mined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of

protection employed. These bits are set by using the WRSR instruction.

Table 1. Instruction Set for the AT25080A/160A/320A/640A

Instruction Name Instruction Format Operation

WREN 0000 X110 Set Write Enable Latch

WRDI 0000 X100 Reset Write Enable Latch

RDSR 0000 X101 Read Status Register

WRSR 0000 X001 Write Status Register

READ 0000 X011 Read Data from Memory Array

WRITE 0000 X010 Write Data to Memory Array

Table 2. Status Register Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

WPEN X X X BP1 BP0 WEN RDY

Table 3. Read Status Register Bit Definition

Bit Definition

Bit 0 (RDY

) Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the write cycle is

in progress.

Bit 1 (WEN) Bit 1= 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates the

device is WRITE ENABLED.

Bit 2 (BP0) See Table 4 on page 10.

Bit 3 (BP1) See Table 4 on page 10.

Bits 4 - 6 are 0s when device is not in an internal write cycle.

Bit 7 (WPEN) See Table 5 on page 10.

Bits 0 - 7 are 1s during an internal write cycle.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

AT25080A-10PI-1.8

Mfr. #:

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AT25080A-10PI-1.8

AT25080A-10PI-1.8

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