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NBSG14MN

P1-P3P4-P6P7-P9P10-P12
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 17
1 Publication Order Number:
NBSG14/D
NBSG14
2.5V/3.3V SiGe Differential
1:4 Clock/Data Driver with
RSECL* Outputs
*Reduced Swing ECL
Description
The NBSG14 is a 1-to-4 clock/data distribution chip, optimized for
ultra-low skew and jitter.
Inputs incorporate internal 50 termination resistors and accept
NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS,
CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV.
All outputs loaded with 50 to V
CC
−2V.
Features
• Maximum Input Clock Frequency up to 12 GHz Typical
• Maximum Input Data Rate up to 12 Gb/s Typical
• 30 ps Typical Rise and Fall Times
• 125 ps Typical Propagation Delay
• RSPECL Output with Operating Range: V
CC
= 2.375 V to 3.465 V
with V
EE
=0V
• RSNECL Output with RSNECL or NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
= −2.375 V to −3.465 V
• RSECL Output Level (400 mV Peak-to-Peak Output),
Differential Output
• 50 Internal Input Termination Resistors
• Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
• These are Pb-Free Devices
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
MARKING DIAGRAMS*
QFN−16
MN SUFFIX
CASE 485G
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
16
SG
14
ALYWG
G
1
1
NBSG14
http://onsemi.com
2
V
EE
Q3 Q3 V
CC
V
EE
Q0 Q0 V
CC
Q1
Q1
Q2
Q2
VTCLK
CLK
CLK
VTCLK
5678
16 15 14 13
12
11
10
9
1
2
3
4
NBSG14
Exposed Pad (EP)
Figure 1. QFN−16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin Name I/O Description
1 VTCLK −
Internal 50 Termination pin. See Table 2.
2 CLK ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input. Internal 75k to V
EE
and 36.5k to V
CC
.
3 CLK ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input. Internal 75k to VEE.
4 VTCLK −
Internal 50 Termination Pin. See Table 2.
5, 16 V
EE
− Negative Supply Voltage. All V
EE
Pins must be Externally Connected to Power Supply to
Guarantee Proper Operation.
6 Q3 RSECL Output
Inverted Differential Output 3. Typically Terminated with 50 to V
TT
= V
CC
− 2 V
7 Q3 RSECL Output
Noninverted Differential Output 3. Typically Terminated with 50 to V
TT
= V
CC
− 2 V
8, 13 V
CC
− Positive Supply Voltage. All V
CC
Pins must be Externally Connected to Power Supply to
Guarantee Proper Operation.
9 Q2 RSECL Output
Inverted Differential Output 2. Typically Terminated with 50 to V
TT
= V
CC
− 2 V
10 Q2 RSECL Output
Noninverted Differential Output 2. Typically Terminated with 50 to V
TT
= V
CC
− 2 V
11 Q1 RSECL Output
Inverted Differential Output 1. Typically Terminated with 50 to V
TT
= V
CC
− 2 V
12 Q1 RSECL Output
Noninverted Differential Output 1. Typically Terminated with 50 to V
TT
= V
CC
− 2 V
14 Q0 RSECL Output
Inverted Differential Output 0. Typically Terminated with 50 to V
TT
= V
CC
− 2 V
15 Q0 RSECL Output
Noninverted Differential Output 0. Typically Terminated with 50 to V
TT
= V
CC
− 2 V
− EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat-sinking
conduit. The pad is not electrically connected to the die but may be electrically and thermally
connected to V
EE
on the PC board.
1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, if no signal
is applied then the device will be susceptible to self-oscillation.
NBSG14
http://onsemi.com
3
50
50
VTCLK
CLK
CLK
VTCLK
V
EE
V
CC
Figure 2. Logic Diagram
75 K 75 K
36.5 K
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
Table 2. INTERFACING OPTIONS
INTERFACING OPTIONS CONNECTIONS
CML Connect VTCLK and VTCLK to V
CC
LVDS Connect VTCLK and VTCLK Together
AC−COUPLED Bias VTCLK and VTCLK Inputs within
Common Mode Range (V
IHCMR
)
RSECL, PECL, NECL Standard ECL Termination Techniques
LVTTL, LVCMOS An External Voltage (V
th
) should be Applied to
the Unused Differential Input. Nominal V
th
is
1.5 V for LVTTL and V
CC
/2 for LVCMOS Inputs.
This Voltage must be within the V
th
Specification.
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor (CLK, CLK)
75 k
Internal Input Pullup Resistor (CLK)
36.5 k
ESD Protection Human Body Model
Machine Model
> 2 kV
> 100 V
Moisture Sensitivity (Note 1) Pb-Free Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 158
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
P1-P3P4-P6P7-P9P10-P12

NBSG14MN

Mfr. #:
Buy NBSG14MN
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 2.5V/3.3V SiGE 1:4
Lifecycle:
New from this manufacturer.
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