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Table 7. DC CHARACTERISTICS, NECL or RSNECL INPUT WITH NECL OUTPUT
(V
CC
= 0 V; V
EE
= −3.465 V to −2.375 V) (Note 15)
Symbo
l
Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
POWER SUPPLY CURRENT
I
EE
Negative Power Supply Current 45 60 75 45 60 75 45 60 75 mA
RSPECL OUTPUTS (Note 16)
V
OH
Output HIGH Voltage −975 −925 −875 −950 −890 −850 −925 −865 −825 mV
V
OUTPP
Output Voltage Amplitude
−3.465 V V
EE
−3.0 V
−3.0 V < V
EE
−2.375 V
350
315
440
405
530
495
350
315
440
405
530
495
350
315
440
405
530
495
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED (Figures 5 & 7) (Note 17)
V
IH
Input HIGH Voltage V
EE
+
1200
V
CC
V
EE
+
1200
V
CC
V
EE
+
1200
V
CC
mV
V
IL
Input LOW Voltage V
EE
V
IH
150
V
EE
V
IH
150
V
EE
V
IH
150
mV
V
th
Input Threshold Voltage Range
(Note 18)
V
EE
+
950
V
CC
75
V
EE
+
950
V
CC
75
V
EE
+
950
V
CC
75
mV
V
ISE
Single-Ended Input Voltage
(V
IH
– V
IL
)
150 2600 150 2600 150 260 mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6 & 8) (Note 19)
V
IHD
Differential Input HIGH Voltage V
EE
+
1200
V
CC
V
EE
+
1200
V
CC
V
EE
+
1200
V
CC
mV
V
ILD
Differential Input LOW Voltage V
EE
V
IHD
75
V
EE
V
IHD
75
V
EE
V
IHD
75
mV
V
ID
Differential Input Voltage
(V
IHD
– V
ILD
)
75 2600 75 2600 75 2600 mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Note 20) (Figure 9)
V
EE
+
1200
0 V
EE
+
1200
0 V
EE
+
1200
0 mV
I
IH
Input HIGH Current (@V
IH
) 80 150 80 150 80 150
A
I
IL
Input LOW Current (@V
IL
) 25 100 25 100 25 100
A
TERMINATION RESISTORS
R
TIN
Internal Input Termination Resistor 45 50 55 45 50 55 45 50 55
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
15.Input and output parameters vary 1:1 with V
CC
.
16.All outputs loaded with 50 to V
CC
− 2.0 V.
17.V
th
, V
IH
, V
IL,
and V
ISE
parameters must be complied with simultaneously.
18.V
th
is applied to the complementary input when operating in single-ended mode. V
th
= (V
IH
− V
IL
) / 2.
19.V
IHD
, V
ILD,
V
ID
and V
IHCMR
parameters must be complied with simultaneously.
20.V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
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Table 8. AC CHARACTERISTICS
(V
CC
= 0 V; V
EE
= −3.465 V to −2.375 V or V
CC
= 2.375 V to 3.465 V; V
EE
= 0 V)
Symbo
l
Characteristic
−40°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
f
max
Maximum Input Clock Frequency
(See Figure 3) (Note 21)
10.5 12 10.5 12 10.5 12 GHz
t
PLH
,
t
PHL
Propagation Delay to
Output Differential
90 125 160 90 125 160 90 125 160 ps
t
SKEW
Duty Cycle Skew (Note 22)
Within-Device Skew (Note 23)
Device-to-Device Skew (Note 24)
3
6
25
15
15
50
3
6
25
15
15
50
3
6
25
15
15
50
ps
t
JITTER
RMS Random Clock Jitter
(Figure 3) (Note 26) f
in
< 10 GHz
Peak-to-Peak Data Dependent Jitter
(Note 27) f
in
< 10 Gb/s
0.2 1 0.2
10
1 0.2 1
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 25)
75 2600 75 2600 75 2600 mV
t
r
t
f
Output Rise/Fall Times Q, Q
(20% − 80%) @ 1 GHz
15 30 55 20 30 55 20 30 55 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
21.Measured using a 500 mV source, 50% duty cycle clock source. All outputs loaded with 50 to V
CC
− 2.0 V. Input edge rates 40 ps
(20% − 80%)
22.See Figure 10. t
SKEW
= |t
PLH
− t
PHL
| for a nominal 50% Differential Clock Input Waveform.
23.Within-Device skew is measured between outputs under identical transitions and conditions on any one device.
24.Device-to-Device skew for identical transitions at identical V
CC
levels.
25.V
INPP
(MAX) cannot exceed V
CC
− V
EE
(applicable only when V
CC
−V
EE
< 2600 mV).
26.Additive RMS Jitter with 50% duty cycle clock signal at 10 GHz.
27.Additive Peak-to-Peak data dependent jitter with NRZ PRBS 2
31
−1 data at 10 Gb/s.
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OUTPUT P−P SPEC
(AMPLITUDE GUARANTEE)
Figure 3. Output Voltage Amplitude (V
OUTPP
) / RMS Jitter vs.
Input Frequency (f
in
) at Ambient Temperature (Typical)
0
100
200
300
400
500
123456789101112
INPUT FREQUENCY (GHz)
OUTPUT VOLTAGE AMPLITUDE (mV)
JITTERout ps (RMS)
RMS JITTER
1
2
3
4
5
6
7
8
9
10
0
OUTPUT AMPLITUDE
Figure 4. Eye Diagram at 10.8 Gbps
(V
CC
− V
EE
= 3.3 V @ 255C with Input Data Pattern of 2^31−1 PRBS.
Total Pk−Pk System Jitter Including Signal Generator is 18 ps.
This Data was taken by Acquiring 7000 Waveforms.)
X = 17 ps/DIV, Y = 53 mV/DIV

NBSG14MN

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 2.5V/3.3V SiGE 1:4
Lifecycle:
New from this manufacturer.
Delivery:
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