OM13488 8-bit GPIO User Manual
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Rev. 1.0 — 11 October 2013
To configure the function pins, apply jumpers between pins 2 & 3 on JP9 and JP11 to
configure device pin 3 as RST and pin 13 as INT . Apply a jumper between pins 1 & 2 on
JP10 to configure device pin 2 as an address.
Then, apply jumpers to JP1 and JP7 to configure the desired I
2
C address. Logic high or logic
low are labeled on the board. Leave JP8 open.
Fig 5. Jumper Configuration for PCA9672, PCAL9538A, PCA9538A, PCA9538
4.5 PCAL6408A, PCA6408A
The PCA(L)6408A devices are level translating, Agile I/0 Expanders with two power supplies,
one address pin, RST and INT . The two power supplies may operate at different voltages
to translate from the I
2
C-bus voltage domain to a higher or lower I/O voltage. JP2 and JP4
may be set to the same or different voltages, or left open and external voltage sources
connected to TP1 and TP2. Unfortunately, there is a slight labeling issue on this board.
Device pin 1 is the VDDI power supply and is permanently connected to JP2 which selects
between VDDP and ground. Use a wire to jumper between pin 2 of JP1 to pin 3 of JP10
which is the board VDDI. See the datasheet for more details on voltage level translation.
Note that the 10K pull up resistors SDA and SCL, R5 and R6, are connected to VDDP which
may cause incorrect current readings if two different supplies are used.
To configure the function pins, apply jumpers between pins 2 & 3 on JP9 and JP11 to
configure device pin 3 as RST and device pin 13 as INT .
There is a slight labeling issue on this board. Device pin 2 is the only address pin and JP10
should jumper pins 1 and 2 to route the address to JP7 (A1 instead of A0).Then, apply a
jumper to JP7 to configure the desired I
2
C address. Logic high or logic low are labeled on the
board. Leave JP8 open.
