MAX531/MAX538/MAX539
+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs
_______________________________________________________________________________________ 7
____________________________Typical Operating Characteristics (continued)
(V
DD
= +5V, V
REFIN
= 2.048V, T
A
= +25°C, unless otherwise noted.)
20
-30
1
MAX531
GAIN AND PHASE vs. FREQUENCY
-10
10
MAX531-10
FREQUENCY (kHz)
GAIN (dB)
10 100
0
-20
800
-180
0
180
GAIN
PHASE
RFB CONNECTED TO AGND (G=2)
RFB CONNECTED TO VOUT (G=1)
PHASE (degrees)
2.0520
2.0490
0 5.0
MAX531 REFERENCE OUTPUT VOLTAGE
vs. REFERENCE LOAD CURRENT
2.0495
2.0515
MAX531-14
REFERENCE LOAD CURRENT (mA)
REFERENCE OUTPUT (V)
3.0
2.0505
2.0500
1.0 2.0 4.0
2.0510
0.5 1.5 2.5 3.5 4.5
V
DD
= ±5V, V
REFIN
= 2V, BIPOLAR CONFIGURATION
A: CS RISING EDGE, 5V/div
B: VOUT, NO LOAD, 1V/div
A
B
NEGATIVE SETTLING TIME (MAX531)
5µs/div
DIGITAL FEEDTHROUGH
A
B
CS = HIGH
A: DIN = 4Vp-p, 100kHz
B: VOUT, 10mV/div
2µs/div
A
B
POSITIVE SETTLING TIME (MAX531)
V
DD
= ±5V, V
REFIN
= 2V, BIPOLAR CONFIGURATION
A: CS RISING EDGE, 5V/div
B: VOUT, NO LOAD, 1V/div
5µs/div
MAX531/MAX538/MAX539
+5V, Low-Power, Voltage-Output
Serial 12-Bit DACs
8 _______________________________________________________________________________________
10
FUNCTION
1
BIPOFF
Bipolar Offset/Gain
Resistor
2 DIN Serial Data Input
3
CLR
Clear. Asynchronously sets
DAC register to 000 hex.
PIN
1
4 SCLK Serial Clock Input
5
CS
Chip Select, active low
6 DOUT
Serial Data Output for
daisy-chaining
7 DGND Digital Ground
2
3
8 AGND Analog Ground
9 REFIN Reference Input
4
5
6
REFOUT
Reference Output,
2.048V
11 V
SS
Negative Power Supply
12 7 VOUT DAC Output
13 8 V
DD
Positive Power Supply
14 RFB Feedback Resistor
MAX531
MAX538
MAX539
NAME
____________________Pin Description
_______________Detailed Description
General DAC Discussion
The MAX531/MAX538/MAX539 use an “inverted” R-2R
ladder network with a single-supply CMOS op amp to con-
vert 12-bit digital data to analog voltage levels (see
Functional Diagram)
. The term “inverted” describes the
ladder network because the REFIN pin in current-output
DACs is the summing junction, or virtual ground, of an op
amp. However, such use would result in the output voltage
being the inverse of the reference voltage. The
MAX531/MAX538/MAX539’s topology makes the output
the same polarity as the reference input.
An internal reset circuit forces the DAC register to reset to
000 hex on power-up. Additionally, a clear CLR pin, when
held low, sets the DAC register to 000 hex. CLR operates
asynchronously and independently from the chip-select
(CS) pin.
Buffer Amplifier
The output buffer is a unity-gain stable, rail-to-rail output,
BiCMOS op amp. Input offset voltage and CMRR are
trimmed to achieve better than 12-bit performance.
Settling time is 25µs to 0.01% of final value. The settling
time is considerably longer when the DAC code is initially
set to 000 hex, because at this code the op amp is com-
pletely debiased. Start from code 001 hex if necessary.
The output is short-circuit protected and can drive a 2k
load with more than 100pF load capacitance.
t
CSH0
t
CSS
t
CH
t
CL
t
CSH1
t
CSW
t
DS
t
DH
t
DO
CS
SCLK
DIN
DOUT
t
CS1
Figure 1. Timing Diagram
Internal Reference (MAX531 only)
The on-chip reference is lesser trimmed to generate 2.048V
at REFOUT. The output stage can source and sink current,
so REFOUT can settle to the correct voltage quickly in
response to code-dependent loading changes. Typically,
source current is 5mA and sink current is 100µA.
REFOUT connects the internal reference to the R-2R DAC
ladder at REFIN. The R-2R ladder draws 50µA maximum
load current. If any other connection is made to REFOUT,
ensure that the total load current is less than 100µA to
avoid gain errors.
For applications requiring very low-noise performance,
connect a 33µF capacitor from REFOUT to AGND. If noise
is not a concern, a lower value capacitor (3.3µF min) may
be used. To reduce noise further, insert a buffered RC filter
between REFOUT and REFIN (Figure 2). The reference
bypass capacitor, C
REFOUT
, is still required for reference
stability. In applications not requiring the reference, con-
nect REFOUT to V
DD
or use the MAX538 or MAX539 (no
internal reference).
External Reference
An external reference in the range (V
SS
+ 2V) to (V
DD
- 2V)
may be used with the MAX531 in dual-supply operation.
With the MAX538/MAX539 or the MAX531 in single-supply
use, the reference must be positive and may not exceed
V
DD
- 2V. The reference voltage determines the DAC’s full-
scale output. The DAC input resistance is code dependent
and is minimum (40k) at code 555 hex and virtually infi-
nite at code 000 hex. REFIN’s input capacitance is also
code dependent and has a 50pF maximum value at sever-
al codes. Because of the code-dependent nature of refer-
ence input impedances, a high-quality, low-output-imped-
ance amplifier (such as the MAX480 low-power, precision
op amp) should be used.
If an upgrade to the internal reference is required, the 2.5V
MAX873A is suitable: ±15mV initial accuracy, TCV
OUT
=
7ppm/°C (max).
Logic Interface
The MAX531/MAX538/MAX539 logic inputs are designed to
be compatible with TTL or CMOS logic levels. However, to
achieve the lowest power dissipation, drive the digital inputs
with rail-to-rail CMOS logic. With TTL logic levels, the power
requirement increases by a factor of approximately 2.
Serial Clock and Update Rate
Figure 1 shows the MAX531/MAX538/MAX539 timing. The
maximum serial clock rate is given by 1 / (t
CH
+ t
CL
),
approximately 14MHz. The digital update rate is limited by
the chip-select period, which is 16 x (t
CH
+ t
CL
) + t
CSW
.
This equals a 1.14µs, or 877kHz, update rate. However, the
DAC settling time to 12 bits is 25µs, which may limit the
update rate to 40kHz for full-scale step transitions.
____________Applications Information
Refer to Figures 3a and 3b for typical operating connec-
tions.
Serial Interface
The MAX531/MAX538/MAX539 use a three-wire serial
interface that is compatible with SPI™, QSPI™
(CPOL = CPHA = 0), and Microwire™ standards as shown
in Figures 4 and 5. The DAC is programmed by writing two
8-bit words (see Figure 1 and the
Functional Diagram
).
Sixteen bits of serial data are clocked into the DAC MSB
first with the MSB preceded by four fill (dummy) bits. The
four dummy bits are not normally needed. They are
required only when DACs are daisy-chained. Data is
clocked in on SCLK’s rising edge while CS is low. The seri-
al input data is held in a 16-bit serial shift register. On CS
’s
rising edge, the 12 least significant bits are transferred to
the DAC register and update the DAC. With CS
high, data
cannot be clocked into the MAX531/MAX538/MAX539.
The MAX531/MAX538/MAX539 input data in 16-bit blocks.
The SPI and Microwire interfaces output data in 8-bit
blocks, thereby requiring two write cycles to input data to
the DAC. The QSPI interface allows variable data input
from eight to 16 bits, and can be loaded into the DAC in
one write cycle.
MAX531/MAX538/MAX539
+5V, Low-Power, Voltage-Output,
Serial 12-Bit DACs
_______________________________________________________________________________________ 9
300
50
1 10 100
100
MAX531-FIG02
FREQUENCY (kHz)
REFERENCE NOISE (µV
RMS
)
150
200
250
0
0.1
1000
TOTAL
REFERENCE
NOISE
R
S
REFOUT
C
REFOUT
C
S
TEK 7A22
C
REFOUT
= 3.3µF
C
REFOUT
= 47µF
SINGLE-POLE ROLLOFF
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
REFERENCE NOISE (mVp-p)
Figure 2. Reference Noise vs. Frequency
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corp.

MAX531BCSD+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC 12-Bit Precision DAC
Lifecycle:
New from this manufacturer.
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