Philips Semiconductors
P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data Rev. 03 — 15 December 2004 43 of 49
9397 750 14471
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1] Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.
[2] When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until V
DD
has reached its specified level. When system power is removed V
DD
will fall below the
minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout
detect circuit may be required to hold the device in reset when V
DD
falls below the minimum specified operating voltage.
Table 10: AC characteristics
V
DD
= 3.0 V to 3.6 V, unless otherwise specified.
T
amb
=
−
40
°
Cto+85
°
C for industrial, unless otherwise specified.
[1]
Symbol Parameter Conditions Variable clock f
osc
=18MHz Unit
Min Max Min Max
f
RCOSC
internal RC oscillator frequency
(nominal f = 7.3728 MHz)
trimmed to ±1%
at T
amb
=25°C
7.189 7.557 7.189 7.557 MHz
f
WDOSC
internal Watchdog oscillator
frequency (nominal f = 400 kHz)
320 520 320 520 kHz
f
osc
oscillator frequency
[2]
0 18 - - MHz
t
CLCL
clock cycle see Figure 13 55 - - - ns
f
CLKP
CLKLP active frequency 0 8 - - MHz
Glitch filter
glitch rejection, P1.5/
RST pin - 50 - 50 ns
signal acceptance, P1.5/
RST pin 125 - 125 - ns
glitch rejection, any pin except
P1.5/
RST
- 15 - 15 ns
signal acceptance, any pin except
P1.5/
RST
50 - 50 - ns
External clock
t
CHCX
HIGH time see Figure 13 22 t
CLCL
− t
CLCX
22 - ns
t
CLCX
LOW time see Figure 13 22 t
CLCL
− t
CHCX
22 - ns
t
CLCH
rise time see Figure 13 -5 -5ns
t
CHCL
fall time see Figure 13 -5 -5ns
Shift register (UART mode 0)
t
XLXL
serial port clock cycle time 16 t
CLCL
- 888 - ns
t
QVXH
output data set-up to clock rising
edge
13 t
CLCL
- 722 - ns
t
XHQX
output data hold after clock rising
edge
-t
CLCL
+ 20 - 75 ns
t
XHDX
input data hold after clock rising
edge
-0 -0ns
t
DVXH
input data valid to clock rising edge 150 - 150 - ns
