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73S8014R-IL/F2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
DS_8014R_012 73S8014R Data Sheet
Rev. 1.0 19
CMDVCC
VCC
I/O
CLK
RSTIN
t
1
t
2
t
0
RST
t
1
= 0.510 ms (timing by 1.5MHz internal oscillator, I/O goes to reception state)
t
2
= RSTIN goes low and CLK becomes active
t
3
= > 0.5μs, CLK active, RST to become the copy of RSTIN
Figure 5: Activation Sequence – RSTIN High When CMDVCC Goes Low
3.7 Deactivation Sequence
Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in the event of
hardware faults. Hardware faults are over-current, VDD fault, VCC fault, and card extraction during the session.
The following steps show the deactivation sequence and the timing of the card control signals when the system
controller sets the CMDVCC high or OFF goes low due to a fault or card removal:
- RST goes low at the end of t
1
.
- CLK is set low at the end of t
2
.
- I/O goes low at the end of t
3
. Out of reception mode.
- VCC is shut down at the end of time t
4
. After a delay t
5
(discharge of the VCC capacitor), VCC is low.
RST
CLK
I/O
VCC
t
1
t
2
t
3
t
4
t
5
CMDVCC
-- OR --
OFF
t
1
= > 0.5μs, timing by 1.5MHz internal Oscillator
t
2
= > 7.5μs
t
3
= > 0.5μs
t
4
= > 0.5μs
t
5
= depends on VCC filter capacitor.
Figure 6: Deactivation Sequence
73S8014R Data Sheet DS_8014R_012
20 Rev. 1.0
3.8 Fault Detection and OFF
There are two different cases that the system controller can monitor the OFF signal: to query regarding the card
presence outside card sessions, or for fault detection during card sessions.
Outside a card session: In this condition, CMDVCC is/are always high, OFF is low if the card is not present, and
high if the card is present. Because it is outside a card session, any fault detection will not act upon the OFF
signal. No deactivation is required during this time.
During a card session: CMDVCC is/are always low, and OFF falls low if the card is extracted or if any fault
detection is detected. At the same time that OFF is set low, the sequencer starts the deactivation process.
Figure 7 shows the timing diagram for the signals CMDVCC, PRES, and OFF during a card session and outside
the card session:
e
the card session:
PRES
OFF
CMDVCC
VCC
PRES
OFF
CMDVCC
VCC
outside card session within card session
OFF is low by
card extracted
OFF is low by
any fault
within card
session
Figure 7: Timing Diagram – Management of the Interrupt Line OFF
3.9 I/O Circuitry and Timing
The state of the I/O pin is low after power on reset and it goes high when the activation sequencer turns on the
I/O reception state. See the Activation Sequence section for details on when the I/O reception is enabled. The
state of I/OUC is high after power on reset.
Within a card session and when the I/O reception state is turned on, the first I/O line on which a falling edge is
detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line rising
edge is detected then both I/O lines return to their neutral state.
Figure 8 shows the state diagram of how the I/O and I/OUC lines are managed to become input or output. The
delay between the I/O signals is shown in Figure 9.
DS_8014R_012 73S8014R Data Sheet
Rev. 1.0 21
Neutral
State
I/OUC
in
I/O
reception
I/OICC
in
No
Yes
No No
No
Yes
No
Yes
I/O
&
not I/OUC
I/OUC
&
not I/O
I/OUC I/O
yesyes
Figure 8: I/O and I/OUC State Diagram
I/O
I/OUC
t
I/O_HL
t
I/O_LH
t
I/OUC_HL
t
I/OUC_LH
Delay from I/O to I/OUC: t
I/O_HL
= 100ns t
I/O_LH
= 25ns
Delay from I/OUC to I/O: t
I/OUC_HL
= 100ns t
I/OUC_LH
= 25ns
Figure 9: I/O – I/OUC Delays – Timing Diagram
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73S8014R-IL/F2

Mfr. #:
Buy 73S8014R-IL/F2
Manufacturer:
Maxim Integrated
Description:
I/O Controller Interface IC Smart Card Interface Comp w/8024
Lifecycle:
New from this manufacturer.
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