73S8014R Data Sheet DS_8014R_012
4 Rev. 1.0
Figures
Figure 1: 73S8014R Block Diagram .......................................................................................................................... 2
Figure 2: 73S8014R 20-SOP Pin Out ........................................................................................................................ 5
Figure 3: 73S8014R – Typical Application Schematic ............................................................................................ 15
Figure 4: Activation Sequence – RSTIN Low When CMDVCC Goes Low ............................................................. 18
Figure 5: Activation Sequence – RSTIN High When CMDVCC Goes Low ............................................................. 19
Figure 6: Deactivation Sequence ............................................................................................................................ 19
Figure 7: Timing Diagram – Management of the Interrupt Line OFF ...................................................................... 20
Figure 8: I/O and I/OUC State Diagram................................................................................................................... 21
Figure 9: I/O – I/OUC Delays – Timing Diagram ..................................................................................................... 21
Figure 10: Open Drain type – OFF .......................................................................................................................... 22
Figure 11: Power Input/Output Circuit, VDD, VPC, VCC ........................................................................................ 22
Figure 12: Smart Card CLK Driver Circuit ............................................................................................................... 23
Figure 13: Smart Card RST Driver Circuit ............................................................................................................... 23
Figure 14: Smart Card IO Interface Circuit .............................................................................................................. 24
Figure 15: Smart Card IOUC Interface Circuit ......................................................................................................... 24
Figure 16: General Input Circuit .............................................................................................................................. 25
Figure 17: Oscillator Circuit ..................................................................................................................................... 25
Figure 18: VDDF_ADJ ............................................................................................................................................. 26
Figure 19: Mechanical Drawing 20-Pin SO Package .............................................................................................. 27
Tables
Table 1: 73S8014R 20-Pin SOP Pin Definitions ....................................................................................................... 6
Table 2: Absolute Maximum Device Ratings ............................................................................................................. 8
Table 3: Recommended Operating Conditions ......................................................................................................... 8
Table 4: Package Thermal Parameters ..................................................................................................................... 9
Table 5: DC Smart Card Interface Requirements ..................................................................................................... 9
Table 6: Digital Signals Characteristics ................................................................................................................... 11
Table 7: DC Characteristics ..................................................................................................................................... 12
Table 8: Voltage Fault Detection Circuits ................................................................................................................ 13
Table 9: Order Numbers and Packaging Marks ...................................................................................................... 28
DS_8014R_012 73S8014R Data Sheet
Rev. 1.0 5
1 Pinout
The 73S8014R is supplied as a 20-pin SO package.
1
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
19
20
CLKDIV1
CLKDIV2
5V/#V
VPC
PRES
I/O
GND
I/OUC
XTALIN
XTALOUT
OFF
VDD
RSTIN
CMDVCC
VCC
RST
CLK
GND
VDDF_ADJ
GND
73S8014R
Figure 2: 73S8014R 20-SOP Pin Out
73S8014R Data Sheet DS_8014R_012
6 Rev. 1.0
Table 1 provides the 73S8014R pin names, pin numbers, type, equivalent circuits and descriptions.
Table 1: 73S8014R 20-Pin SOP Pin Definitions
Pin Name
Pin
Number
Type
Equivalent
Circuit
Description
Card Interface
I/O 14 IO Figure 14
Card I/O: Data signal to/from card. Includes an 11k pull-up
resistor to V
CC.
RST 15 O Figure 13 Card reset: provides reset (RST) signal to card.
CLK 17 O Figure 12
Card clock: provides clock signal (CLK) to card. The rate of this
clock is determined by the external crystal frequency or frequency
of the external clock signal applied on XTALIN and CLKDIV
selections.
PRES 19 I Figure 16
Card Presence switch: active high indicates card is present.
Includes a high-impedance pull-down current source.
VCC 18 PSO Figure 11
Card power supply – logically controlled by sequencer, output of
LDO regulator. Requires an external filter capacitor to the card
GND.
GND 16 GND Card ground.
Host Processor Interface
CMDVCC
6 I Figure 16
Command VCC (negative assertion): Logic low on this pin causes
the LDO regulator to ramp the V
CC
supply to the card and initiates
a card activation sequence, if a card is present.
5V/#V 7 I Figure 16
5 volt / 3 volt card selection: Logic one selects 5 volts for V
CC
and
card interface, logic low selects 3 volt operation. When the part is
to be used with a single card voltage, this pin should be tied to
either GND or V
DD
. However, it includes a high impedance pull-up
resistor to default this pin high (selection of 5V card) when not
connected. This pin shall not be changed when CMDVCC is low.
CLKDIV1
CLKDIV2
20
5
I Figure 16
Sets the divide ratio from the XTAL oscillator (or external clock
input) to the card clock. These pins include a pull-up resistor for
CLKDIV1 and CLKLDIV2 to provide a default rate of divide by
two.
CLKDIV1 CLKDIV2 CLOCK RATE
0 0 XTALIN/8
0 1 XTALIN/4
1 1 XTALIN/2
1 0 XTALIN
OFF 1 O Figure 10
Interrupt signal to the processor. Active Low - Multi-function
indicating fault conditions and card presence. Open drain output
configuration – It includes an internal 20k pull-up to V
DD.
RSTIN 2 I Figure 16 Reset Input: This signal is the reset command to the card.
I/OUC 3 IO Figure 15
System controller data I/O to/from the card. Includes an 11K
pull-up resistor to V
DD.

73S8014R-IL/F2

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
I/O Controller Interface IC Smart Card Interface Comp w/8024
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union